| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | intel_alm: Add multiply signedness to cells | Dan Ravensloft | 2020-08-26 | 1 | -3/+4 |
| * | Unify verilog style | Miodrag Milanovic | 2019-10-18 | 1 | -7/+5 |
| * | Share common tests | Miodrag Milanovic | 2019-10-18 | 1 | -0/+11 |
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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