| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | tests: aiger test for wire->start_offset != 0 | Eddie Hung | 2020-05-02 | 1 | -0/+5 |
| * | tests/aiger: write Yosys output | Eddie Hung | 2020-01-07 | 1 | -2/+2 |
| * | tests: use optional ABCEXTERNAL when specified | Gabriel L. Somlo | 2019-06-27 | 1 | -2/+12 |
| * | Make tests/aiger less chatty | Clifford Wolf | 2019-06-19 | 1 | -4/+6 |
| * | Add some more comments | Eddie Hung | 2019-06-10 | 1 | -1/+6 |
| * | Test *.aag too, by using *.aig as reference | Eddie Hung | 2019-06-07 | 1 | -0/+19 |
| * | Use ABC to convert AIGER to Verilog, then sat against Yosys | Eddie Hung | 2019-06-07 | 1 | -21/+15 |
| * | Support and differentiate between ASCII and binary AIG testing | Eddie Hung | 2019-02-08 | 1 | -1/+5 |
| * | Rename ASCII tests | Eddie Hung | 2019-02-06 | 1 | -0/+20 |
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index : iCE40/yosys | |
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