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* tests: aiger test for wire->start_offset != 0Eddie Hung2020-05-021-0/+5
* tests/aiger: write Yosys outputEddie Hung2020-01-071-2/+2
* tests: use optional ABCEXTERNAL when specifiedGabriel L. Somlo2019-06-271-2/+12
* Make tests/aiger less chattyClifford Wolf2019-06-191-4/+6
* Add some more commentsEddie Hung2019-06-101-1/+6
* Test *.aag too, by using *.aig as referenceEddie Hung2019-06-071-0/+19
* Use ABC to convert AIGER to Verilog, then sat against YosysEddie Hung2019-06-071-21/+15
* Support and differentiate between ASCII and binary AIG testingEddie Hung2019-02-081-1/+5
* Rename ASCII testsEddie Hung2019-02-061-0/+20