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* opt_expr: Remove -clkinv option, make it the default.Marcelina Kościelnicka2020-07-312-2/+2
| | | | | Adds -noclkinv option just in case the old behavior was actually useful to someone.
* synth_ice40: Use opt_dff.Marcelina Kościelnicka2020-07-304-142/+6
| | | | | | | | | The main part is converting ice40_dsp to recognize the new FF types created in opt_dff instead of trying to recognize the mux patterns on its own. The fsm call has been moved upwards because the passes cannot deal with $dffe/$sdff*, and other optimizations don't help it much anyway.
* synth_xilinx: Use opt_dff.Marcelina Kościelnicka2020-07-301-17/+12
| | | | | | | | | The main part is converting xilinx_dsp to recognize the new FF types created in opt_dff instead of trying to recognize the patterns on its own. The fsm call has been moved upwards because the passes cannot deal with $dffe/$sdff*, and other optimizations don't help it much anyway.
* intel_alm: direct M10K instantiationDan Ravensloft2020-07-277-39/+127
| | | | This reverts commit a3a90f6377f251d3b6c5898eb1543f8832493bb8.
* intel_alm: increase abc9 -WDan Ravensloft2020-07-261-1/+1
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* Merge pull request #2294 from Ravenslofty/intel_alm_timingsclairexen2020-07-234-72/+91
|\ | | | | intel_alm: add additional ABC9 timings
| * intel_alm: add additional ABC9 timingsDan Ravensloft2020-07-234-72/+91
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* | Remove EXPLICIT_CARRY logic.Keith Rothman2020-07-233-150/+2
|/ | | | | | | The symbiflow-arch-defs tool chain no longer needs the EXPLICIT_CARRY within yosys itself. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* sf2: Emit CLKINT even if -clkbuf not passedMarcelina Kościelnicka2020-07-171-2/+6
| | | | This restores pre #2229 behavior.
* Merge pull request #2274 from YosysHQ/mwk/anlogic-ff-fixMiodrag Milanović2020-07-171-12/+12
|\ | | | | anlogic: Fix FF mapping.
| * anlogic: Fix FF mapping.Marcelina Kościelnicka2020-07-171-12/+12
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* | Merge pull request #2229 from Ravenslofty/sf2_remove_sf2_iobsclairexen2020-07-164-214/+135
|\ \ | |/ |/| sf2: replace sf2_iobs with {clkbuf,iopad}map
| * sf2: replace sf2_iobs with {clkbuf,iopad}mapDan Ravensloft2020-07-094-214/+135
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* | Merge pull request #2238 from YosysHQ/mwk/dfflegalize-anlogicMiodrag Milanović2020-07-163-50/+35
|\ \ | | | | | | anlogic: Use dfflegalize.
| * | anlogic: Use dfflegalize.Marcelina Kościelnicka2020-07-143-50/+35
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* | Merge pull request #2226 from YosysHQ/mwk/nuke-efinix-gbufMiodrag Milanović2020-07-165-122/+11
|\ \ | | | | | | efinix: Nuke efinix_gbuf in favor of clkbufmap.
| * | efinix: Nuke efinix_gbuf in favor of clkbufmap.Marcelina Kościelnicka2020-07-045-122/+11
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* | | achronix: Use dfflegalize.Marcelina Kościelnicka2020-07-141-1/+1
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* | | intel: Use dfflegalize.Marcelina Kościelnicka2020-07-138-178/+17
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* | | Revert "intel_alm: direct M10K instantiation"Lofty2020-07-137-122/+38
| | | | | | | | | | | | This reverts commit 09ecb9b2cf3ab76841d30712bf70dafc6d47ef67.
* | | xilinx: Fix srl regression.Marcelina Kościelnicka2020-07-121-2/+2
| | | | | | | | | | | | | | | | | | | | | Of standard yosys cells, xilinx_srl only works on $_DFF_?_ and $_DFFE_?P_, which get upgraded to $_SDFFE_?P?P_ by dfflegalize at the point where xilinx_srl is called for non-abc9. Fix this by running ff_map.v first, resulting in FDRE cells, which are handled correctly.
* | | sf2: Use dfflegalize.Marcelina Kościelnicka2020-07-092-44/+13
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* | | xilinx: Use dfflegalize.Marcelina Kościelnicka2020-07-096-484/+131
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* | | efinix: Use dfflegalize.Marcelina Kościelnicka2020-07-062-15/+53
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* | | gowin: Use dfflegalize.Marcelina Kościelnicka2020-07-062-145/+41
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* | | intel_alm: direct M10K instantiationDan Ravensloft2020-07-057-38/+122
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* | | synth_gowin: ABC9 supportDan Ravensloft2020-07-052-34/+340
| | | | | | | | | | | | | | | This adds ABC9 support for synth_gowin; drastically improving synthesis quality.
* | | Merge pull request #2236 from YosysHQ/mwk/dfflegalize-ice40Marcelina Kościelnicka2020-07-054-208/+24
|\ \ \ | | | | | | | | ice40: Use dfflegalize.
| * | | ice40: Use dfflegalize.Marcelina Kościelnicka2020-07-054-208/+24
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* | | | ecp5: Use dfflegalize.Marcelina Kościelnicka2020-07-054-254/+96
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* | | | Merge pull request #2232 from YosysHQ/mwk/gowin-sim-initMarcelina Kościelnicka2020-07-051-8/+8
|\ \ \ \ | | | | | | | | | | gowin: Fix INIT values in sim library.
| * | | | gowin: Fix INIT values in sim library.Marcelina Kościelnicka2020-07-051-8/+8
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* | | | intel_alm: DSP inferenceDan Ravensloft2020-07-056-9/+186
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* | | gowin: replace determine_init with setundefDan Ravensloft2020-07-043-74/+1
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* | | synth_intel_alm: Use dfflegalize.Marcelina Kościelnicka2020-07-042-121/+9
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* | Improve MISTRAL_FF specify rulesDan Ravensloft2020-07-041-5/+4
| | | | | | | | Co-authored-by: Eddie Hung <eddie@fpgeh.com>
* | intel_alm: compose $__MISTRAL_FF_SYNCONLY from MISTRAL_FFEddie Hung2020-07-042-47/+2
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* | intel_alm: add $__ prefix to MISTRAL_FF_SYNCONLYEddie Hung2020-07-044-4/+4
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* | intel_alm: ABC9 sequential optimisationsDan Ravensloft2020-07-047-19/+149
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* simcells: Fix reset polarity for $_DLATCH_???_ cells.Marcelina Kościelnicka2020-06-302-5/+5
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* Update dff2dffe, dff2dffs, zinit to new FF types.Marcelina Kościelnicka2020-06-2316-128/+128
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* Add new FF types to simplemap.Marcelina Kościelnicka2020-06-231-1/+1
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* Add new builtin FF typesMarcelina Kościelnicka2020-06-233-0/+2293
| | | | | | | | | | | | | | The new types include: - FFs with async reset and enable (`$adffe`, `$_DFFE_[NP][NP][01][NP]_`) - FFs with sync reset (`$sdff`, `$_SDFF_[NP][NP][01]_`) - FFs with sync reset and enable, reset priority (`$sdffs`, `$_SDFFE_[NP][NP][01][NP]_`) - FFs with sync reset and enable, enable priority (`$sdffce`, `$_SDFFCE_[NP][NP][01][NP]_`) - FFs with async reset, set, and enable (`$dffsre`, `$_DFFSRE_[NP][NP][NP][NP]_`) - latches with reset or set (`$adlatch`, `$_DLATCH_[NP][NP][01]_`) The new FF types are not actually used anywhere yet (this is left for future commits).
* Use C++11 final/override keywords.whitequark2020-06-1831-95/+95
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* Fix Verilator sim warnings: 1 BLKSEQ and 3 WIDTHXark2020-06-141-7/+7
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* intel_alm: fix DFFE matchingDan Ravensloft2020-06-111-1/+1
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* Do not optimize away FFs in "prep" and Verific fron-endClaire Wolf2020-06-091-2/+2
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improveEddie Hung2020-06-041-1/+1
|\ | | | | abc9: -dff improvements
| * abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_Eddie Hung2020-05-291-1/+1
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* | Add flooring division operatorXiretza2020-05-282-0/+71
| | | | | | | | | | | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $divfloor cell provides this flooring division. This commit also fixes the handling of $div in opt_expr, which was previously optimized as if it was $divfloor.
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