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* Added GP_DFFS, GP_DFFR, and GP_DFFSRClifford Wolf2016-03-234-21/+76
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* Added GP_DFF INIT parameterClifford Wolf2016-03-232-0/+4
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* Improvements in synth_greenpak4, added -part optionClifford Wolf2016-03-211-30/+25
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* Added black box modules for all the 7-series design elements (as listed in ↵Clifford Wolf2016-03-194-0/+3441
| | | | ug953)
* Run dffsr2dff in synth_xilinxClifford Wolf2016-02-131-0/+2
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* Work around DDR dout sim glitches in ice40 SB_IO sim modelClifford Wolf2016-02-071-1/+7
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* Added dffsr2dffClifford Wolf2016-02-021-0/+2
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* Progress in cell library documentationClifford Wolf2016-02-011-0/+238
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* Added "abc -luts" option, Improved Xilinx logic mappingClifford Wolf2016-02-011-2/+2
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* Re-run ice40_opt in "synth_ice40 -abc2"Clifford Wolf2015-12-221-1/+4
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* Improvements in ice40_optClifford Wolf2015-12-221-5/+16
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* Bugfix in ice40_ffinitClifford Wolf2015-12-221-2/+2
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* Improved ice40_ffinitClifford Wolf2015-12-221-1/+22
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* Run opt_const before check in default scriptsClifford Wolf2015-12-222-0/+4
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* Added "synth_ice40 -abc2"Clifford Wolf2015-12-081-0/+11
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* Merge pull request #108 from cseed/masterClifford Wolf2015-12-071-1/+3
|\ | | | | Added LO to ICESTORM_LC for LUT cascade route.
| * Added LO to ICESTORM_LC for LUT cascade route.Cotton Seed2015-12-061-1/+3
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* | Added ice40_ffinit passClifford Wolf2015-11-263-0/+145
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* | Fixed WE/RE usage in iCE40 BRAM mappingClifford Wolf2015-11-241-8/+8
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* | Fixed iCE40 SB_IO OUTPUT_ENABLE vs. outena_q handlingClifford Wolf2015-11-061-2/+2
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* | Bugfix in Xilinx LUT mappingClifford Wolf2015-10-301-1/+1
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* | Progress on cell help messagesClifford Wolf2015-10-201-18/+114
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* | Progress on cell help messagesClifford Wolf2015-10-172-53/+106
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* | Added "prep" commandClifford Wolf2015-10-142-0/+157
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* | Added more cell descriptionsClifford Wolf2015-10-141-0/+85
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* | Added first help messages for cell typesClifford Wolf2015-10-144-0/+292
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* | Added examples/ top-level directoryClifford Wolf2015-10-1314-279/+0
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* | Added read-enable to memory modelClifford Wolf2015-09-256-29/+36
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* | Added nlutmapClifford Wolf2015-09-181-2/+2
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* | Renamed GreenPAK4 cells, improved GP4 DFF mappingClifford Wolf2015-09-185-9/+50
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* | Fixed copy&paste typo in synth_greenpak4Clifford Wolf2015-09-161-3/+3
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* | Added GreenPAK4 skeletonClifford Wolf2015-09-164-0/+297
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* | Fixed ice40 handling of negclk RAM40Clifford Wolf2015-09-102-12/+12
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* | Switched to Python 3Clifford Wolf2015-08-224-10/+4
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* Another bugfix for ice40 and xilinx brams_init make rulesClifford Wolf2015-08-164-9/+9
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* Fixed Makefile rules for generated share filesClifford Wolf2015-08-162-2/+13
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* Added $tribuf and $_TBUF_ sim modelsClifford Wolf2015-08-162-0/+20
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* Added tribuf commandClifford Wolf2015-08-161-0/+2
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* Added $tribuf and $_TBUF_ cell typesClifford Wolf2015-08-161-1/+1
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* Another block of spelling fixesLarry Doolittle2015-08-143-4/+4
| | | | Smaller this time
* Adjust makefiles to work with out-of-tree buildsClifford Wolf2015-08-124-22/+3
| | | | This is based on work done by Larry Doolittle
* Improved handling of "keep" attributes in hierarchical designs in opt_cleanClifford Wolf2015-08-121-2/+1
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* Added iCE40 WARMBOOT cellMarcus Comstedt2015-08-061-0/+10
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* Added WORDS parameter to $meminitClifford Wolf2015-07-311-1/+2
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* Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle)Clifford Wolf2015-07-271-1/+0
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* iCE40 DFF sim models: init Q regs to 0Clifford Wolf2015-07-201-20/+43
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* Avoid tristate warning for blackbox ice40/cells_sim.vClifford Wolf2015-07-181-0/+2
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* Improved liberty file test caseClifford Wolf2015-07-061-1/+2
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* Added "synth -nofsm"Clifford Wolf2015-07-021-1/+10
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* Fixed trailing whitespacesClifford Wolf2015-07-0213-30/+30
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