iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Merge pull request #1601 from YosysHQ/eddie/synth_retime	Eddie Hung	2020-01-02	1	-3/+3
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\| *	Update doc that "-retime" calls abc with "-dff -D 1"	Eddie Hung	2019-12-30	1	-1/+1
\| *	Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""	Eddie Hung	2019-12-30	1	-2/+2
* \|	ifdef __ICARUS__ -> ifndef YOSYS	Eddie Hung	2020-01-01	1	-6/+6
* \|	Update timings for Xilinx S7 cells	Eddie Hung	2019-12-30	1	-15/+35
* \|	Merge remote-tracking branch 'origin/master' into iopad_default	Miodrag Milanovic	2019-12-28	8	-10/+368
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\| *	Merge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgen	Marcin Kościelnicki	2019-12-25	3	-3/+6
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\| \| *	xilinx_dsp: Initial DSP48A/DSP48A1 support.	Marcin Kościelnicki	2019-12-22	3	-3/+6
\| * \|	xilinx: Test our DSP48A/DSP48A1 simulation models.	Marcin Kościelnicki	2019-12-23	5	-7/+362
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* \|	Addressed review comments	Miodrag Milanovic	2019-12-21	1	-2/+3
* \|	iopad no op for compatibility with old scripts	Miodrag Milanovic	2019-12-21	1	-0/+3
* \|	Make iopad option default for all xilinx flows	Miodrag Milanovic	2019-12-21	1	-14/+5
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*	Add abc9_arrival times for RAM{32,64}M	Eddie Hung	2019-12-20	1	-24/+10
*	Add RAM{32,64}M to abc9_map.v	Eddie Hung	2019-12-20	1	-0/+78
*	Revert "Optimise write_xaiger"	Eddie Hung	2019-12-20	1	-5/+0
*	Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup	Eddie Hung	2019-12-19	1	-0/+5
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\| *	techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger	Eddie Hung	2019-12-06	1	-0/+5
* \|	xilinx: Add simulation models for remaining CLB primitives.	Marcin Kościelnicki	2019-12-19	3	-156/+210
* \|	xilinx_dffopt: Keep order of LUT inputs.	Marcin Kościelnicki	2019-12-19	1	-16/+30
* \|	xilinx: Add xilinx_dffopt pass (#1557)	Marcin Kościelnicki	2019-12-18	6	-22/+389
* \|	xilinx: Improve flip-flop handling.	Marcin Kościelnicki	2019-12-18	4	-38/+228
* \|	Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram	Eddie Hung	2019-12-16	3	-12/+301
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\| * \	Merge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into eddie/xil...	Eddie Hung	2019-12-16	1	-2/+8
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\| \| * \|	Populate DID/DOD even if unused	Eddie Hung	2019-12-16	1	-2/+8
\| * \| \|	Rename *RAM{32,64}M rules to RAM{32X2,64X1}Q	Eddie Hung	2019-12-16	2	-6/+6
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\| * \|	Disable RAM16X1D match rule; carry-over from LUT4 arches	Eddie Hung	2019-12-13	1	-6/+9
\| * \|	RAM64M8 to also have [5:0] for address	Eddie Hung	2019-12-13	1	-8/+8
\| * \|	Add RAM32X6SDP and RAM64X3SDP modes	Eddie Hung	2019-12-12	2	-8/+120
\| * \|	Fix RAM64M model to have 6 bit address bus	Eddie Hung	2019-12-12	1	-4/+4
\| * \|	Add memory rules for RAM16X1D, RAM32M, RAM64M	Eddie Hung	2019-12-12	2	-0/+168
* \| \|	Add unconditional match blocks for force RAM	Eddie Hung	2019-12-16	1	-4/+36
* \| \|	Update xc7/xcu bram rules	Eddie Hung	2019-12-16	1	-8/+4
* \| \|	Removing fixed attribute value to !ramstyle rules	Diego H	2019-12-15	1	-4/+4
* \| \|	Merging attribute rules into a single match block; Adding tests	Diego H	2019-12-15	1	-18/+12
* \| \|	Refactoring memory attribute matching based on IEEE 1364.1 and Tool specific	Diego H	2019-12-13	1	-0/+19
* \| \|	Merge pull request #1533 from dh73/bram_xilinx	Eddie Hung	2019-12-13	1	-6/+9
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\| * \|	Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test.	Diego H	2019-12-12	1	-5/+5
\| * \|	Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1	Diego H	2019-12-12	1	-2/+2
\| * \|	Merge https://github.com/YosysHQ/yosys into bram_xilinx	Diego H	2019-12-12	5	-633/+868
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\| * \|	Adjusting Vivado's BRAM min bits threshold for RAMB18E1	Diego H	2019-11-27	1	-2/+5
* \| \|	abc9_map.v: fix Xilinx LUTRAM	Eddie Hung	2019-12-12	1	-6/+6
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* \|	xilinx: Add tristate buffer mapping. (#1528)	Marcin Kościelnicki	2019-12-04	2	-9/+16
* \|	xilinx: Add models for LUTRAM cells. (#1537)	Marcin Kościelnicki	2019-12-04	3	-624/+831
* \|	xilinx: Add missing blackbox cell for BUFPLL.	Marcin Kościelnicki	2019-11-29	2	-0/+21
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*	xilinx: Add simulation models for IOBUF and OBUFT.	Marcin Kościelnicki	2019-11-26	3	-25/+30
*	clkbufmap: Add support for inverters in clock path.	Marcin Kościelnicki	2019-11-25	1	-1/+5
*	xilinx: Use INV instead of LUT1 when applicable	Marcin Kościelnicki	2019-11-25	1	-2/+6
*	xilinx: Add simulation models for MULT18X18* and DSP48A*.	Marcin Kościelnicki	2019-11-19	3	-132/+516
*	synth_xilinx: Merge blackbox primitive libraries.	Marcin Kościelnicki	2019-11-06	11	-23234/+29820
*	xilinx: Add URAM288 mapping for xcup	David Shah	2019-10-23	5	-2/+92