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* Added output args to synth_ice40Clifford Wolf2015-05-261-2/+2
* Verific build fixesClifford Wolf2015-05-171-2/+2
* Improved xilinx "bram1" testClifford Wolf2015-04-091-1/+2
* Added memory_bram "make_outreg" featureClifford Wolf2015-04-091-0/+2
* Xilinx DRAMS: RAM64X1D, RAM128X1DClifford Wolf2015-04-093-13/+67
* Towards DRAM support in Xilinx flowClifford Wolf2015-04-095-0/+78
* Added support for initialized xilinx bramsClifford Wolf2015-04-0610-91/+314
* Added Xilinx test case for initialized bramsClifford Wolf2015-04-064-0/+80
* Added Xilinx bram black-box modulesClifford Wolf2015-04-063-0/+322
* Added "dffinit", Support for initialized Xilinx DFFClifford Wolf2015-04-041-5/+6
* Added "stat" to "synth" and "synth_xilinx"Clifford Wolf2015-02-151-0/+2
* Added final checks to "synth" and "synth_xilinx"Clifford Wolf2015-02-151-0/+10
* Disabled (unused) Xilinx tristate buffersClifford Wolf2015-02-041-6/+6
* no support for 6-series xilinx devicesClifford Wolf2015-02-011-1/+1
* Removed old XST-based xilinx examplesClifford Wolf2015-02-0111-208/+0
* Added Xilinx example for Basys3 boardClifford Wolf2015-02-019-1/+84
* Added missing ports and parameters to xilinx bramsClifford Wolf2015-02-011-4/+18
* Fixed xilinx FDSE sim modelClifford Wolf2015-01-241-2/+2
* Various cleanups in xilinx techlibClifford Wolf2015-01-187-9/+110
* Refactoring of memory_bram and xilinx bramsClifford Wolf2015-01-183-468/+55
* Added synth_xilinx -retime -flattenClifford Wolf2015-01-171-2/+28
* Added MUXCY and XORCY support to synth_xilinxClifford Wolf2015-01-174-2/+106
* Added dff2dffe to synth_xilinxClifford Wolf2015-01-161-0/+2
* Added more FF types to xilinx/cells.vClifford Wolf2015-01-161-25/+28
* Fixed xilinx bram clock inverted configClifford Wolf2015-01-161-21/+35
* Added FF cells to xilinx/cells_sim.vClifford Wolf2015-01-161-116/+116
* Added Xilinx MUXF7 and MUXF8 supportClifford Wolf2015-01-152-2/+30
* Various cleanups in synth_xilinx commandClifford Wolf2015-01-131-54/+8
* Added add_share_file Makefile macroClifford Wolf2015-01-081-13/+4
* added minimalistic xilinx sim modelsClifford Wolf2015-01-081-0/+150
* More Xilinx bram cleanupsClifford Wolf2015-01-071-14/+14
* Cleanups in xilinx bram descriptionsClifford Wolf2015-01-072-36/+36
* Xilinx RAMB36/RAMB18 memory_bram support completeClifford Wolf2015-01-063-16/+320
* Towards Xilinx bram supportClifford Wolf2015-01-063-24/+65
* small fix in xilinx/brams.vClifford Wolf2015-01-061-5/+5
* Towards Xilinx bram supportClifford Wolf2015-01-064-25/+176
* Various small improvements to synth_xilinxClifford Wolf2015-01-061-8/+6
* Towards Xilinx bram supportClifford Wolf2015-01-062-13/+41
* Towards Xilinx bram supportClifford Wolf2015-01-063-6/+10
* Towards Xilinx bram supportClifford Wolf2015-01-057-19/+172
* Towards Xilinx bram supportClifford Wolf2015-01-043-13/+182
* Progress in memory_bramClifford Wolf2014-12-311-3/+3
* Added memory_bram (not functional yet)Clifford Wolf2014-12-311-0/+20
* namespace YosysClifford Wolf2014-09-271-1/+5
* Renamed $lut ports to follow A-Y naming schemeClifford Wolf2014-08-151-18/+18
* Added "make PRETTY=1"Clifford Wolf2014-07-241-2/+2
* Added "techmap -share_map" optionClifford Wolf2013-11-241-4/+4
* Fixed xilinx/example_sim_counter test benchClifford Wolf2013-11-241-1/+1
* Added more generic _TECHMAP_ wire mechanism to techmap passClifford Wolf2013-11-231-1/+1
* [EXAMPLES] Ported the mojo counter example to Zynq ZED board.James Walmsley2013-10-274-0/+56
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