| Commit message (Expand) | Author | Age | Files | Lines |
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| | | * | | | | | | | | | | Merge branch 'master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 1 | -11/+22 |
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| | | | * | | | | | | | | | Put abc_* attributes above port | Eddie Hung | 2019-08-23 | 1 | -7/+14 |
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| | | * | | | | | | | | | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 5 | -30/+39 |
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| | | * | | | | | | | | | move attributes to wires | Marcin Kościelnicki | 2019-08-13 | 6 | -283/+537 |
| | | * | | | | | | | | | minor review fixes | Marcin Kościelnicki | 2019-08-13 | 1 | -1/+1 |
| | | * | | | | | | | | | review fixes | Marcin Kościelnicki | 2019-08-13 | 1 | -18/+27 |
| | | * | | | | | | | | | Add clock buffer insertion pass, improve iopadmap. | Marcin Kościelnicki | 2019-08-13 | 6 | -71/+220 |
| * | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-20 | 5 | -24/+39 |
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| | * | | | | | | | | | | Merge pull request #1209 from YosysHQ/eddie/synth_xilinx | Eddie Hung | 2019-08-20 | 4 | -16/+19 |
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| | | * | | | | | | | | | Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx | Eddie Hung | 2019-08-20 | 3 | -6/+6 |
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| | | * | | | | | | | | | Update Makefile too | Eddie Hung | 2019-07-18 | 1 | -2/+2 |
| | | * | | | | | | | | | Work in progress for renaming labels/options in synth_xilinx | Eddie Hung | 2019-07-18 | 3 | -14/+17 |
| | * | | | | | | | | | | Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro | Eddie Hung | 2019-08-19 | 1 | -2/+2 |
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| | * | | | | | | | | | Attach abc_scc_break, abc_carry_{in,out} attr to ports not modules | Eddie Hung | 2019-08-16 | 1 | -8/+20 |
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| * | | | | | | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp | Eddie Hung | 2019-08-15 | 1 | -1/+5 |
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| | * | | | | | | | | xilinx: Rework labels for faster Verilator testing | David Shah | 2019-08-13 | 1 | -1/+5 |
| * | | | | | | | | | Add assign PCOUT = P to DSP48E1 | Eddie Hung | 2019-08-13 | 1 | -0/+2 |
| * | | | | | | | | | Add DSP_A_MAXWIDTH_PARTIAL, refactor | Eddie Hung | 2019-08-13 | 1 | -1/+1 |
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| * | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-12 | 1 | -1/+1 |
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| | * | | | | | | | stoi -> atoi | Eddie Hung | 2019-08-07 | 1 | -1/+1 |
| * | | | | | | | | Pack partial-product adder DSP48E1 packing | Eddie Hung | 2019-08-09 | 1 | -0/+2 |
| * | | | | | | | | Remove signed from ports in +/xilinx/dsp_map.v | Eddie Hung | 2019-08-08 | 1 | -1/+1 |
| * | | | | | | | | Combine techmap calls | Eddie Hung | 2019-08-08 | 1 | -2/+1 |
| * | | | | | | | | Move xilinx_dsp to before alumacc | Eddie Hung | 2019-08-08 | 1 | -6/+4 |
| * | | | | | | | | INMODE is 5 bits | Eddie Hung | 2019-08-08 | 1 | -1/+1 |
| * | | | | | | | | Fix copy-pasta typo | Eddie Hung | 2019-08-08 | 1 | -2/+2 |
| * | | | | | | | | DSP48E1 sim model: add SIMD tests | David Shah | 2019-08-08 | 3 | -3/+113 |
| * | | | | | | | | DSP48E1 model: test CE inputs | David Shah | 2019-08-08 | 2 | -7/+17 |
| * | | | | | | | | DSP48E1 sim model: fix seq tests and add preadder tests | David Shah | 2019-08-08 | 2 | -6/+91 |
| * | | | | | | | | DSP48E1 sim model: seq test working | David Shah | 2019-08-08 | 3 | -16/+60 |
| * | | | | | | | | DSP48E1 sim model: Comb, no pre-adder, mode working | David Shah | 2019-08-08 | 2 | -8/+13 |
| * | | | | | | | | [wip] sim model testing | David Shah | 2019-08-08 | 4 | -15/+77 |
| * | | | | | | | | [wip] sim model testing | David Shah | 2019-08-08 | 3 | -40/+360 |
| * | | | | | | | | [wip] DSP48E1 sim model improvements | David Shah | 2019-08-07 | 1 | -6/+82 |
| * | | | | | | | | [wip] DSP48E1 sim model improvements | David Shah | 2019-08-06 | 1 | -23/+120 |
| * | | | | | | | | [wip] DSP48E1 sim model improvements | David Shah | 2019-08-06 | 1 | -8/+75 |
| * | | | | | | | | Change $__softmul back to $mul | Eddie Hung | 2019-08-01 | 1 | -0/+1 |
| * | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-01 | 2 | -5/+5 |
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| | * | | | | | | | RST -> RSTBRST for RAMB8BWER | Eddie Hung | 2019-07-29 | 1 | -3/+3 |
| | * | | | | | | | xilinx: Fix missing cell name underscore in cells_map.v | David Shah | 2019-07-25 | 1 | -2/+2 |
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| * | | | | | | | Add params | Eddie Hung | 2019-07-18 | 1 | -0/+6 |
| * | | | | | | | Use single DSP_SIGNEDONLY macro | Eddie Hung | 2019-07-18 | 1 | -1/+1 |
| * | | | | | | | Make all operands signed | Eddie Hung | 2019-07-17 | 1 | -1/+1 |
| * | | | | | | | Update comment | Eddie Hung | 2019-07-17 | 1 | -5/+3 |
| * | | | | | | | Signedness | Eddie Hung | 2019-07-16 | 2 | -8/+8 |
| * | | | | | | | Revert drop down to 24x16 multipliers for all | Eddie Hung | 2019-07-16 | 2 | -4/+4 |
| * | | | | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp | Eddie Hung | 2019-07-16 | 3 | -5/+9 |
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| | * | | | | | | | xilinx: Add correct signed behaviour to DSP48E1 model | David Shah | 2019-07-16 | 1 | -1/+1 |
| | * | | | | | | | xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 si... | David Shah | 2019-07-16 | 2 | -4/+8 |
| * | | | | | | | | Add support for {A,B,P}REG in DSP48E1 | Eddie Hung | 2019-07-16 | 1 | -5/+21 |
