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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-08 10:44:35 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-08 10:44:35 -0700 |
| commit | 57b2e4b9c1dda6d092e261f90a311087c62d0bc4 (patch) | |
| tree | 3604c2a978a0f5daf33644947ee7cf8fdf4ea5aa /techlibs/xilinx | |
| parent | 13cc106cf7409570936f441af2cc133896f4ecb4 (diff) | |
| download | yosys-57b2e4b9c1dda6d092e261f90a311087c62d0bc4.tar.gz yosys-57b2e4b9c1dda6d092e261f90a311087c62d0bc4.tar.bz2 yosys-57b2e4b9c1dda6d092e261f90a311087c62d0bc4.zip | |
INMODE is 5 bits
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/dsp_map.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/dsp_map.v b/techlibs/xilinx/dsp_map.v index 3d7b09d69..423e12fbe 100644 --- a/techlibs/xilinx/dsp_map.v +++ b/techlibs/xilinx/dsp_map.v @@ -32,7 +32,7 @@ module \$__MUL25X18 (input signed [24:0] A, input signed [17:0] B, output signed .D(24'b0), .P(P_48), - .INMODE(4'b0000), + .INMODE(5'b00000), .ALUMODE(4'b0000), .OPMODE(7'b000101), .CARRYINSEL(3'b000), |