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xilinx
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Author
Age
Files
Lines
*
output reg Q -> output Q to suppress warning
Eddie Hung
2019-12-04
1
-8
/
+8
*
abc9_map.v to do `zinit' and make INIT = 1'b0
Eddie Hung
2019-12-04
1
-70
/
+112
*
Add abc9_init wire, attach to abc9_flop cell
Eddie Hung
2019-12-03
1
-2
/
+12
*
Revert "Add INIT value to abc9_control"
Eddie Hung
2019-12-03
1
-8
/
+8
*
techmap abc_unmap.v before xilinx_srl -fixed
Eddie Hung
2019-12-03
1
-6
/
+5
*
Add INIT value to abc9_control
Eddie Hung
2019-12-02
1
-8
/
+8
*
clkpart -unpart into 'finalize'
Eddie Hung
2019-11-28
1
-3
/
+4
*
ean call after abc{,9}
Eddie Hung
2019-11-27
1
-1
/
+2
*
Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dff
Eddie Hung
2019-11-27
3
-25
/
+30
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*
xilinx: Add simulation models for IOBUF and OBUFT.
Marcin Kościelnicki
2019-11-26
3
-25
/
+30
*
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Move 'clean' from map_luts to finalize
Eddie Hung
2019-11-26
1
-1
/
+1
*
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-11-25
2
-3
/
+11
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clkbufmap: Add support for inverters in clock path.
Marcin Kościelnicki
2019-11-25
1
-1
/
+5
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*
xilinx: Use INV instead of LUT1 when applicable
Marcin Kościelnicki
2019-11-25
1
-2
/
+6
*
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Special abc9_clock wire to contain only clock signal
Eddie Hung
2019-11-25
1
-12
/
+10
*
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For abc9, run clkpart before ff_map and after abc9
Eddie Hung
2019-11-23
1
-0
/
+2
*
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Merge branch 'eddie/xaig_dff_adff' into xaig_dff
Eddie Hung
2019-11-21
1
-12
/
+16
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*
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Do not drop async control signals in abc_map.v
Eddie Hung
2019-11-19
1
-12
/
+16
*
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Add blackbox model for $__ABC9_FF_ so that clock partitioning works
Eddie Hung
2019-11-20
1
-0
/
+3
*
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Fix INIT values
Eddie Hung
2019-11-20
1
-4
/
+4
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/
/
*
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-11-19
22
-23020
/
+30968
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\
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*
xilinx: Add simulation models for MULT18X18* and DSP48A*.
Marcin Kościelnicki
2019-11-19
3
-132
/
+516
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*
synth_xilinx: Merge blackbox primitive libraries.
Marcin Kościelnicki
2019-11-06
11
-23234
/
+29820
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*
xilinx: Add URAM288 mapping for xcup
David Shah
2019-10-23
5
-2
/
+92
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*
xilinx: Add support for UltraScale[+] BRAM mapping
David Shah
2019-10-23
7
-416
/
+1062
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*
xilinx: Support multiplier mapping for all families.
Marcin Kościelnicki
2019-10-22
9
-9
/
+269
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*
Merge pull request #1452 from nakengelhardt/fix_dsp_mem_reg
Clifford Wolf
2019-10-22
1
-0
/
+1
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*
Call memory_dff before DSP mapping to reserve registers (fixes #1447)
N. Engelhardt
2019-10-17
1
-0
/
+1
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*
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Makefile: don't assume python is called `python3`
Sean Cross
2019-10-19
1
-1
/
+1
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/
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*
xilinx: Add simulation model for IBUFG.
Marcin Kościelnicki
2019-10-10
5
-33
/
+14
*
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-10-08
1
-5
/
+9
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*
Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9
Eddie Hung
2019-10-08
11
-112
/
+121
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*
Merge branch 'master' into eddie/abc_to_abc9
Eddie Hung
2019-10-04
4
-181
/
+9
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*
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Add comment on why partial multipliers are 18x18
Eddie Hung
2019-10-04
1
-4
/
+8
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*
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Fix typo in check_label()
Eddie Hung
2019-10-04
1
-1
/
+1
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/
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*
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Cleanup
Eddie Hung
2019-10-07
1
-7
/
+2
*
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Rename $currQ to $abc9_currQ
Eddie Hung
2019-10-07
1
-46
/
+46
*
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Update comments in abc9_map.v
Eddie Hung
2019-10-07
1
-131
/
+57
*
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Remove -D_ABC9
Eddie Hung
2019-10-07
1
-2
/
+0
*
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Do not require changes to cells_sim.v; try and work out comb model
Eddie Hung
2019-10-05
4
-230
/
+200
*
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abc -> abc9
Eddie Hung
2019-10-04
1
-3
/
+3
*
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-10-04
4
-181
/
+9
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\
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*
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Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9`
Eddie Hung
2019-10-04
1
-2
/
+6
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*
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Remove DSP48E1 from *_cells_xtra.v
Eddie Hung
2019-10-04
3
-178
/
+2
*
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Use read_args for read_verilog
Eddie Hung
2019-10-04
1
-3
/
+6
*
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Fix merge issues
Eddie Hung
2019-10-04
2
-9
/
+10
*
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Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff
Eddie Hung
2019-10-04
11
-139
/
+154
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*
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Rename abc_* names/attributes to more precisely be abc9_*
Eddie Hung
2019-10-04
11
-111
/
+120
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/
*
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English
Eddie Hung
2019-10-03
1
-3
/
+3
*
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More fixes
Eddie Hung
2019-10-01
1
-16
/
+16
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