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* t:$dff* -> t:$dff t:$dffeEddie Hung2019-04-041-2/+2
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* -nosrl meant when -nobramEddie Hung2019-04-031-1/+1
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* Remove duplicate STARTUPE2Eddie Hung2019-04-031-1/+0
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* Disable shregmap in synth_xilinx if -retimeEddie Hung2019-04-031-3/+3
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* synth_xilinx to use shregmap with -minlen 3Eddie Hung2019-03-251-2/+2
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* Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-03-222-24/+31
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| * xilinx: Add keep attribute where appropriateDavid Shah2019-03-222-25/+31
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Add '-nosrl' option to synth_xilinxEddie Hung2019-03-211-6/+16
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* | Fine tune cells_map.vEddie Hung2019-03-201-19/+15
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* | Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable lengthEddie Hung2019-03-191-53/+20
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* | Add support for variable length Xilinx SRL > 128Eddie Hung2019-03-191-11/+67
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* | Restore original synth_xilinx commandsEddie Hung2019-03-191-1/+2
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* | Fix spacingEddie Hung2019-03-191-1/+1
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* | Fix INIT for variable length SRs that have been bumped up oneEddie Hung2019-03-191-1/+1
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* | Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-03-191-2/+4
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| * Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873Clifford Wolf2019-03-191-2/+4
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Only accept <128 for variable length, only if $shiftx exclusiveEddie Hung2019-03-161-5/+1
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* | Cleanup synth_xilinxEddie Hung2019-03-152-3/+2
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* | WorkingEddie Hung2019-03-152-47/+78
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* | Reverse bits in INIT parameter for Xilinx, since MSB is shifted firstEddie Hung2019-03-141-16/+32
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* | MisspellEddie Hung2019-03-141-1/+1
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* | Revert "Add shregmap -init_msb_first and use in synth_xilinx"Eddie Hung2019-03-141-3/+2
| | | | | | | | This reverts commit 26ecbc1aee1dca1c186ab2b51835d74f67bc3e75.
* | Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-03-1410-177/+571
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| * Merge pull request #842 from litghost/merge_upstreamClifford Wolf2019-03-0510-176/+570
| |\ | | | | | | Changes required for VPR place and route in synth_xilinx
| | * Revert BRAM WRITE_MODE changes.Keith Rothman2019-03-041-12/+12
| | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| | * Revert FF models to include IS_x_INVERTED parameters.Keith Rothman2019-03-011-6/+34
| | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| | * Use singular for disabling of DRAM or BRAM inference.Keith Rothman2019-03-011-13/+13
| | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| | * Modify arguments to match existing style.Keith Rothman2019-03-011-6/+6
| | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| | * Changes required for VPR place and route synth_xilinx.Keith Rothman2019-03-0111-221/+587
| | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * | Use "write_edif -pvector bra" for Xilinx EDIF filesClifford Wolf2019-03-051-1/+1
| |/ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add shregmap -init_msb_first and use in synth_xilinxEddie Hung2019-03-141-2/+2
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* | Fix cells_map for SRLEddie Hung2019-03-141-19/+17
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* | Move shregmap until after first techmapEddie Hung2019-03-131-2/+2
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* | Refactor $__SHREG__ in cells_map.vEddie Hung2019-03-131-32/+24
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* | Remove SRL16/32 from cells_xtraEddie Hung2019-02-282-18/+2
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* | Add SRL16 and SRL32 sim modelsEddie Hung2019-02-281-0/+39
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* | Fix SRL16/32 techmap off-by-oneEddie Hung2019-02-281-18/+24
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* | synth_xilinx to call shregmap with enable supportEddie Hung2019-02-282-24/+29
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* | synth_xilinx to use shregmap with -params tooEddie Hung2019-02-282-22/+19
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* | synth_xilinx to now have shregmap call after dff2dffeEddie Hung2019-02-281-0/+2
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* | Add techmap rule for $__SHREG_DFF_P_ to SRL16/32Eddie Hung2019-02-281-0/+71
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* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-021-1/+1
| | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually.
* Add support for Xilinx PS7 blockEddie Hung2018-11-102-0/+624
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* xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.Tim 'mithro' Ansell2018-10-081-3/+2
| | | | | Then if targeting vpr map all the Xilinx specific LUTs back into generic Yosys LUTs.
* Add inout ports to cells_xtra.vClifford Wolf2018-10-042-2/+14
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* xilinx: Adding missing inout IO port to IOBUFTim Ansell2018-10-031-0/+1
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* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
| | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
* Improving vpr output support.Tim 'mithro' Ansell2018-04-182-3/+36
| | | | | | | * Support output BLIF for Xilinx architectures. * Support using .names in BLIF for Xilinx architectures. * Use the same `NO_LUT` define in both `synth_ice40` and `synth_xilinx`.
* Squelch trailing whitespace, including meta-whitespaceLarry Doolittle2018-03-111-8/+8
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* Add Xilinx RAM64X1D and RAM128X1D simulation modelsClifford Wolf2018-03-074-23/+30
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