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* | | | | | | | | synth_xilinx: cleanup helpEddie Hung2020-01-281-6/+4
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* | | | | | | | | synth_xilinx: fix help when no active_design; fixes #1664Eddie Hung2020-01-281-2/+3
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* | | | | | | | | xilinx: Add simulation model for DSP48 (Virtex 4).Marcin Kościelnicki2020-01-296-45/+534
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* | | | | | | | | Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_lutsEddie Hung2020-01-281-62/+37
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| * | | | | | | | | xilinx/ice40/ecp5: undo permuting LUT masks in lut_mapEddie Hung2020-01-271-62/+37
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* | | | | | | | | Fix unresolved conflict from #1573Eddie Hung2020-01-281-1/+1
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* | | | | | | | | Merge pull request #1573 from YosysHQ/eddie/xilinx_tristateN. Engelhardt2020-01-281-0/+3
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| * | | | | | | | Duplicate tribuf call, credit to @mwkmwkmwkEddie Hung2019-12-131-1/+0
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| * | | | | | | | synth_xilinx: error out if tristate without '-iopad'Eddie Hung2019-12-121-0/+4
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* | | | | | | | | Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0Eddie Hung2020-01-221-1/+1
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* | | | | | | | | Merge remote-tracking branch 'origin/master' into eddie/abc9_refactorEddie Hung2020-01-212-125/+88
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| * | | | | | | | Deprecate `_CLB_CARRY from +/xilinx/arith_map.v since #1623Eddie Hung2020-01-172-119/+82
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| * | | | | | | | +/xilinx/arith_map.v fix $lcu ruleEddie Hung2020-01-171-6/+6
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* | | | | | | | | Merge remote-tracking branch 'origin/master' into eddie/abc9_refactorEddie Hung2020-01-151-1/+1
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| * | | | | | | Merge pull request #1636 from YosysHQ/eddie/fix_synth_xilinx_WMiodrag Milanović2020-01-151-1/+1
| |\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | synth_xilinx: fix default W value for non-xc7
| | * | | | | | | synth_xilinx: fix default W value for non-xc7Eddie Hung2020-01-141-1/+1
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* | | | | | | | | Adding (* techmap_autopurge *) to FD* in abc9_map.vEddie Hung2020-01-141-8/+8
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* | | | | | | | Merge pull request #1623 from YosysHQ/mmicko/edif_attrMiodrag Milanović2020-01-141-1/+1
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| * | | | | | | Use CARRY4 for abc1 as well, preventing issues with VivadoMiodrag Milanovic2020-01-101-1/+1
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* | | | | | | Another conflictEddie Hung2020-01-111-1/+0
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* | | | | | | synth_xilinx: synth_xilinx.abc9.xc7.W to replace XC7_WIRE_DELAY macroEddie Hung2020-01-101-4/+11
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* | | | | / Fix abc9_xc7.box commentsEddie Hung2020-01-071-7/+14
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* | | | | Merge branch 'master' of github.com:YosysHQ/yosysEddie Hung2020-01-066-152/+642
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| * \ \ \ \ Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2020-01-065-1674/+509
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| * | | | | Fix spacingEddie Hung2020-01-021-1/+1
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| * | | | synth_xilinx -dff to work with abc tooEddie Hung2020-01-021-6/+14
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| * | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2020-01-022-24/+44
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| * | | | | Update commentsEddie Hung2020-01-021-11/+6
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| * | | | | abc9 -keepff -> -dff; refactor dff operationsEddie Hung2020-01-022-58/+58
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| * | | | | Clamp -46ps for FDPE* tooEddie Hung2020-01-011-2/+2
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| * | | | | Restore abc9 -keepffEddie Hung2020-01-012-86/+6
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| * | | | | Re-arrange FD orderEddie Hung2019-12-313-182/+182
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| * | | | | Cleanup xilinx boxesEddie Hung2019-12-312-391/+425
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| * | | | | Update abc9_xc7.box commentsEddie Hung2019-12-311-18/+18
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| * | | | | FDCE ports to be alphabeticalEddie Hung2019-12-311-3/+3
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| * | | | | Fix attributes on $__ABC9_ASYNC[01] whiteboxEddie Hung2019-12-311-2/+2
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| * | | | | Fix incorrect $__ABC9_ASYNC[01] boxEddie Hung2019-12-311-2/+2
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| * | | | | Do not offset FD* box timings due to -46ps TsuEddie Hung2019-12-301-12/+21
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| * | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-308-21/+374
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| * | | | | | Tidy up abc9_map.vEddie Hung2019-12-301-103/+103
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| * | | | | | Add "synth_xilinx -dff" option, cleanup abc9Eddie Hung2019-12-302-2/+98
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| * | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-201-24/+10
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| * \ \ \ \ \ \ Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-204-172/+240
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| * | | | | | | | Add RAM{32,64}M to abc9_map.vEddie Hung2019-12-191-0/+78
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| * | | | | | | | Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_tEddie Hung2019-12-195-36/+55
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| * | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-1912-77/+967
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| * | | | | | | | | abc9_map.v: fix Xilinx LUTRAMEddie Hung2019-12-121-6/+6
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| * | | | | | | | | Fix commentEddie Hung2019-12-091-1/+1
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| * | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-065-633/+868
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| * | | | | | | | | Remove creation of $abc9_control_wireEddie Hung2019-12-061-16/+6
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