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xilinx
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Author
Age
Files
Lines
*
Squelch trailing whitespace, including meta-whitespace
Larry Doolittle
2018-03-11
1
-8
/
+8
*
Add Xilinx RAM64X1D and RAM128X1D simulation models
Clifford Wolf
2018-03-07
4
-23
/
+30
*
Add techlibs/xilinx/lut2lut.v
Clifford Wolf
2017-07-10
2
-0
/
+66
*
Added "yosys -D" feature
Clifford Wolf
2016-04-21
1
-1
/
+1
*
Added black box modules for all the 7-series design elements (as listed in ug...
Clifford Wolf
2016-03-19
4
-0
/
+3441
*
Run dffsr2dff in synth_xilinx
Clifford Wolf
2016-02-13
1
-0
/
+2
*
Added "abc -luts" option, Improved Xilinx logic mapping
Clifford Wolf
2016-02-01
1
-2
/
+2
*
Bugfix in Xilinx LUT mapping
Clifford Wolf
2015-10-30
1
-1
/
+1
*
Added examples/ top-level directory
Clifford Wolf
2015-10-13
7
-77
/
+0
*
Added read-enable to memory model
Clifford Wolf
2015-09-25
3
-19
/
+23
*
Switched to Python 3
Clifford Wolf
2015-08-22
2
-5
/
+2
*
Another bugfix for ice40 and xilinx brams_init make rules
Clifford Wolf
2015-08-16
2
-5
/
+5
*
Fixed Makefile rules for generated share files
Clifford Wolf
2015-08-16
1
-1
/
+7
*
Adjust makefiles to work with out-of-tree builds
Clifford Wolf
2015-08-12
1
-6
/
+2
*
Fixed trailing whitespaces
Clifford Wolf
2015-07-02
3
-6
/
+6
*
Added output args to synth_ice40
Clifford Wolf
2015-05-26
1
-2
/
+2
*
Verific build fixes
Clifford Wolf
2015-05-17
1
-2
/
+2
*
Improved xilinx "bram1" test
Clifford Wolf
2015-04-09
1
-1
/
+2
*
Added memory_bram "make_outreg" feature
Clifford Wolf
2015-04-09
1
-0
/
+2
*
Xilinx DRAMS: RAM64X1D, RAM128X1D
Clifford Wolf
2015-04-09
3
-13
/
+67
*
Towards DRAM support in Xilinx flow
Clifford Wolf
2015-04-09
5
-0
/
+78
*
Added support for initialized xilinx brams
Clifford Wolf
2015-04-06
10
-91
/
+314
*
Added Xilinx test case for initialized brams
Clifford Wolf
2015-04-06
4
-0
/
+80
*
Added Xilinx bram black-box modules
Clifford Wolf
2015-04-06
3
-0
/
+322
*
Added "dffinit", Support for initialized Xilinx DFF
Clifford Wolf
2015-04-04
1
-5
/
+6
*
Added "stat" to "synth" and "synth_xilinx"
Clifford Wolf
2015-02-15
1
-0
/
+2
*
Added final checks to "synth" and "synth_xilinx"
Clifford Wolf
2015-02-15
1
-0
/
+10
*
Disabled (unused) Xilinx tristate buffers
Clifford Wolf
2015-02-04
1
-6
/
+6
*
no support for 6-series xilinx devices
Clifford Wolf
2015-02-01
1
-1
/
+1
*
Removed old XST-based xilinx examples
Clifford Wolf
2015-02-01
11
-208
/
+0
*
Added Xilinx example for Basys3 board
Clifford Wolf
2015-02-01
9
-1
/
+84
*
Added missing ports and parameters to xilinx brams
Clifford Wolf
2015-02-01
1
-4
/
+18
*
Fixed xilinx FDSE sim model
Clifford Wolf
2015-01-24
1
-2
/
+2
*
Various cleanups in xilinx techlib
Clifford Wolf
2015-01-18
7
-9
/
+110
*
Refactoring of memory_bram and xilinx brams
Clifford Wolf
2015-01-18
3
-468
/
+55
*
Added synth_xilinx -retime -flatten
Clifford Wolf
2015-01-17
1
-2
/
+28
*
Added MUXCY and XORCY support to synth_xilinx
Clifford Wolf
2015-01-17
4
-2
/
+106
*
Added dff2dffe to synth_xilinx
Clifford Wolf
2015-01-16
1
-0
/
+2
*
Added more FF types to xilinx/cells.v
Clifford Wolf
2015-01-16
1
-25
/
+28
*
Fixed xilinx bram clock inverted config
Clifford Wolf
2015-01-16
1
-21
/
+35
*
Added FF cells to xilinx/cells_sim.v
Clifford Wolf
2015-01-16
1
-116
/
+116
*
Added Xilinx MUXF7 and MUXF8 support
Clifford Wolf
2015-01-15
2
-2
/
+30
*
Various cleanups in synth_xilinx command
Clifford Wolf
2015-01-13
1
-54
/
+8
*
Added add_share_file Makefile macro
Clifford Wolf
2015-01-08
1
-13
/
+4
*
added minimalistic xilinx sim models
Clifford Wolf
2015-01-08
1
-0
/
+150
*
More Xilinx bram cleanups
Clifford Wolf
2015-01-07
1
-14
/
+14
*
Cleanups in xilinx bram descriptions
Clifford Wolf
2015-01-07
2
-36
/
+36
*
Xilinx RAMB36/RAMB18 memory_bram support complete
Clifford Wolf
2015-01-06
3
-16
/
+320
*
Towards Xilinx bram support
Clifford Wolf
2015-01-06
3
-24
/
+65
*
small fix in xilinx/brams.v
Clifford Wolf
2015-01-06
1
-5
/
+5
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