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Author
Age
Files
Lines
*
Fix spacing
Eddie Hung
2020-01-02
1
-1
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+1
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synth_xilinx -dff to work with abc too
Eddie Hung
2020-01-02
1
-6
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+14
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2020-01-02
2
-24
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+44
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Merge pull request #1601 from YosysHQ/eddie/synth_retime
Eddie Hung
2020-01-02
1
-3
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+3
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Update doc that "-retime" calls abc with "-dff -D 1"
Eddie Hung
2019-12-30
1
-1
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+1
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Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""
Eddie Hung
2019-12-30
1
-2
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+2
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ifdef __ICARUS__ -> ifndef YOSYS
Eddie Hung
2020-01-01
1
-6
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+6
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Update timings for Xilinx S7 cells
Eddie Hung
2019-12-30
1
-15
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+35
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Update comments
Eddie Hung
2020-01-02
1
-11
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+6
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abc9 -keepff -> -dff; refactor dff operations
Eddie Hung
2020-01-02
2
-58
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+58
*
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Clamp -46ps for FDPE* too
Eddie Hung
2020-01-01
1
-2
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+2
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Restore abc9 -keepff
Eddie Hung
2020-01-01
2
-86
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+6
*
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Re-arrange FD order
Eddie Hung
2019-12-31
3
-182
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+182
*
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Cleanup xilinx boxes
Eddie Hung
2019-12-31
2
-391
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+425
*
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Update abc9_xc7.box comments
Eddie Hung
2019-12-31
1
-18
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+18
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FDCE ports to be alphabetical
Eddie Hung
2019-12-31
1
-3
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+3
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Fix attributes on $__ABC9_ASYNC[01] whitebox
Eddie Hung
2019-12-31
1
-2
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+2
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Fix incorrect $__ABC9_ASYNC[01] box
Eddie Hung
2019-12-31
1
-2
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+2
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Do not offset FD* box timings due to -46ps Tsu
Eddie Hung
2019-12-30
1
-12
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+21
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-12-30
8
-21
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+374
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Merge remote-tracking branch 'origin/master' into iopad_default
Miodrag Milanovic
2019-12-28
8
-10
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+368
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Merge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgen
Marcin Kościelnicki
2019-12-25
3
-3
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+6
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xilinx_dsp: Initial DSP48A/DSP48A1 support.
Marcin Kościelnicki
2019-12-22
3
-3
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+6
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xilinx: Test our DSP48A/DSP48A1 simulation models.
Marcin Kościelnicki
2019-12-23
5
-7
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+362
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Addressed review comments
Miodrag Milanovic
2019-12-21
1
-2
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+3
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iopad no op for compatibility with old scripts
Miodrag Milanovic
2019-12-21
1
-0
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+3
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Make iopad option default for all xilinx flows
Miodrag Milanovic
2019-12-21
1
-14
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+5
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*
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Tidy up abc9_map.v
Eddie Hung
2019-12-30
1
-103
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+103
*
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Add "synth_xilinx -dff" option, cleanup abc9
Eddie Hung
2019-12-30
2
-2
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+98
*
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-12-20
1
-24
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+10
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Add abc9_arrival times for RAM{32,64}M
Eddie Hung
2019-12-20
1
-24
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+10
*
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-12-20
4
-172
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+240
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Add RAM{32,64}M to abc9_map.v
Eddie Hung
2019-12-20
1
-0
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+78
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Revert "Optimise write_xaiger"
Eddie Hung
2019-12-20
1
-5
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+0
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Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup
Eddie Hung
2019-12-19
1
-0
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+5
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techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger
Eddie Hung
2019-12-06
1
-0
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+5
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xilinx: Add simulation models for remaining CLB primitives.
Marcin Kościelnicki
2019-12-19
3
-156
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+210
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xilinx_dffopt: Keep order of LUT inputs.
Marcin Kościelnicki
2019-12-19
1
-16
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+30
*
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Add RAM{32,64}M to abc9_map.v
Eddie Hung
2019-12-19
1
-0
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+78
*
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Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t
Eddie Hung
2019-12-19
5
-36
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+55
*
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-12-19
12
-77
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+967
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xilinx: Add xilinx_dffopt pass (#1557)
Marcin Kościelnicki
2019-12-18
6
-22
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+389
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xilinx: Improve flip-flop handling.
Marcin Kościelnicki
2019-12-18
4
-38
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+228
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Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram
Eddie Hung
2019-12-16
3
-12
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+301
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Merge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into eddie/xil...
Eddie Hung
2019-12-16
1
-2
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+8
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Populate DID/DOD even if unused
Eddie Hung
2019-12-16
1
-2
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+8
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Rename *RAM{32,64}M rules to RAM{32X2,64X1}Q
Eddie Hung
2019-12-16
2
-6
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+6
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/
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Disable RAM16X1D match rule; carry-over from LUT4 arches
Eddie Hung
2019-12-13
1
-6
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+9
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RAM64M8 to also have [5:0] for address
Eddie Hung
2019-12-13
1
-8
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+8
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Add RAM32X6SDP and RAM64X3SDP modes
Eddie Hung
2019-12-12
2
-8
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+120
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