| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325) | Eddie Hung | 2020-09-23 | 1 | -0/+1 |
| | | | | | | | | | | | | * xilinx: eliminate SCCs from DSP48E1 model * xilinx: add SCC test for DSP48E1 * Update techlibs/xilinx/cells_sim.v * xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1 Have a test that checks it works through ABC9 when enabled | ||||
| * | xilinx: Support multiplier mapping for all families. | Marcin Kościelnicki | 2019-10-22 | 1 | -0/+49 |
| This supports several older families that are not yet supported for actual logic synthesis — the intention is to add them soon. | |||||
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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