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* xilinx: Add simulation model for DSP48 (Virtex 4).Marcin Koƛcielnicki2020-01-293-0/+304
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* xilinx: Test our DSP48A/DSP48A1 simulation models.Marcin Koƛcielnicki2019-12-234-4/+359
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* Add pattern detection support for DSP48E1 model, check against vendorEddie Hung2019-09-182-4/+59
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* DSP48E1 sim model: add SIMD testsDavid Shah2019-08-082-2/+112
| | | | Signed-off-by: David Shah <dave@ds0.me>
* DSP48E1 model: test CE inputsDavid Shah2019-08-081-2/+9
| | | | Signed-off-by: David Shah <dave@ds0.me>
* DSP48E1 sim model: fix seq tests and add preadder testsDavid Shah2019-08-082-6/+91
| | | | Signed-off-by: David Shah <dave@ds0.me>
* DSP48E1 sim model: seq test workingDavid Shah2019-08-082-10/+47
| | | | Signed-off-by: David Shah <dave@ds0.me>
* DSP48E1 sim model: Comb, no pre-adder, mode workingDavid Shah2019-08-081-6/+10
| | | | Signed-off-by: David Shah <dave@ds0.me>
* [wip] sim model testingDavid Shah2019-08-083-13/+75
| | | | Signed-off-by: David Shah <dave@ds0.me>
* [wip] sim model testingDavid Shah2019-08-082-0/+311
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Improved xilinx "bram1" testClifford Wolf2015-04-091-1/+2
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* Added support for initialized xilinx bramsClifford Wolf2015-04-065-19/+90
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* Added Xilinx test case for initialized bramsClifford Wolf2015-04-064-0/+80
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* Various cleanups in xilinx techlibClifford Wolf2015-01-181-0/+2
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* Refactoring of memory_bram and xilinx bramsClifford Wolf2015-01-181-3/+7
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* Cleanups in xilinx bram descriptionsClifford Wolf2015-01-071-4/+4
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* Xilinx RAMB36/RAMB18 memory_bram support completeClifford Wolf2015-01-061-1/+1
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* Towards Xilinx bram supportClifford Wolf2015-01-061-10/+49
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* Towards Xilinx bram supportClifford Wolf2015-01-062-1/+3
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* Towards Xilinx bram supportClifford Wolf2015-01-061-11/+18
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* Towards Xilinx bram supportClifford Wolf2015-01-062-4/+8
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* Towards Xilinx bram supportClifford Wolf2015-01-054-0/+148