iCE40/yosys - clone of https://github.com/YosysHQ/yosys

	Commit message (Expand)	Author	Age	Files	Lines
*	Fixing old e-mail addresses and deadnames	Claire Xenia Wolf	2021-06-08	1	-1/+1
*	Add force_downto and force_upto wire attributes.	Marcelina Kościelnicka	2020-05-19	1	-0/+1
*	xilinx: Initial support for LUT4 devices.	Marcin Kościelnicki	2020-02-07	1	-26/+28
*	xilinx/ice40/ecp5: undo permuting LUT masks in lut_map	Eddie Hung	2020-01-27	1	-62/+37
*	xilinx: Use INV instead of LUT1 when applicable	Marcin Kościelnicki	2019-11-25	1	-2/+6
*	Really permute Xilinx LUT mappings as default LUT6.I5:A6	Eddie Hung	2019-06-18	1	-16/+16
*	Revert "Fix (do not) permute LUT inputs, but permute mux selects"	Eddie Hung	2019-06-18	1	-33/+31
*	Fix (do not) permute LUT inputs, but permute mux selects	Eddie Hung	2019-06-18	1	-31/+33
*	Fix copy-pasta issue	Eddie Hung	2019-06-17	1	-9/+8
*	Permute INIT for +/xilinx/lut_map.v	Eddie Hung	2019-06-17	1	-32/+58
*	Changes required for VPR place and route synth_xilinx.	Keith Rothman	2019-03-01	1	-0/+94