| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Work in progress for renaming labels/options in synth_xilinx | Eddie Hung | 2019-07-18 | 1 | -60/+0 |
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| * | Add RAM32X1D support | Eddie Hung | 2019-06-24 | 1 | -0/+20 |
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| * | Add "min bits" and "min wports" to xilinx dram rules | Eddie Hung | 2019-05-23 | 1 | -0/+4 |
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| * | Added memory_bram "make_outreg" feature | Clifford Wolf | 2015-04-09 | 1 | -0/+2 |
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| * | Xilinx DRAMS: RAM64X1D, RAM128X1D | Clifford Wolf | 2015-04-09 | 1 | -3/+20 |
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| * | Towards DRAM support in Xilinx flow | Clifford Wolf | 2015-04-09 | 1 | -0/+17 |
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index : iCE40/yosys | |
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