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path: root/techlibs/xilinx/cells_xtra.py
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* Remove DSP48E1 from *_cells_xtra.vEddie Hung2019-10-041-2/+2
* Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}Eddie Hung2019-09-301-2/+2
* Use extractinv for synth_xilinx -iseMarcin Kościelnicki2019-09-191-3/+20
* xilinx: Make blackbox library family-dependent.Marcin Kościelnicki2019-09-151-45/+479
* move attributes to wiresMarcin Kościelnicki2019-08-131-0/+257