iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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\| *	Add additional cells sim models for core 7-series primatives.	Keith Rothman	2019-04-09	1	-0/+57
* \|	Merge remote-tracking branch 'origin/master' into xc7srl	Eddie Hung	2019-03-14	1	-0/+65
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\| *	Revert FF models to include IS_x_INVERTED parameters.	Keith Rothman	2019-03-01	1	-6/+34
\| *	Changes required for VPR place and route synth_xilinx.	Keith Rothman	2019-03-01	1	-33/+70
* \|	Add SRL16 and SRL32 sim models	Eddie Hung	2019-02-28	1	-0/+39
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*	Add Xilinx RAM64X1D and RAM128X1D simulation models	Clifford Wolf	2018-03-07	1	-0/+30
*	Disabled (unused) Xilinx tristate buffers	Clifford Wolf	2015-02-04	1	-6/+6
*	Added Xilinx example for Basys3 board	Clifford Wolf	2015-02-01	1	-1/+5
*	Fixed xilinx FDSE sim model	Clifford Wolf	2015-01-24	1	-2/+2
*	Added MUXCY and XORCY support to synth_xilinx	Clifford Wolf	2015-01-17	1	-0/+4
*	Added FF cells to xilinx/cells_sim.v	Clifford Wolf	2015-01-16	1	-116/+116
*	added minimalistic xilinx sim models	Clifford Wolf	2015-01-08	1	-0/+150