| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth_xilinx: Initial Spartan 6 block RAM inference support. | Marcin Kościelnicki | 2019-07-11 | 1 | -0/+16 |
| * | Squelch trailing whitespace, including meta-whitespace | Larry Doolittle | 2018-03-11 | 1 | -8/+8 |
| * | Switched to Python 3 | Clifford Wolf | 2015-08-22 | 1 | -4/+1 |
| * | Another bugfix for ice40 and xilinx brams_init make rules | Clifford Wolf | 2015-08-16 | 1 | -4/+4 |
| * | Added support for initialized xilinx brams | Clifford Wolf | 2015-04-06 | 1 | -0/+37 |
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index : iCE40/yosys | |
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