| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Big rework; flop info now mostly in cells_sim.v | Eddie Hung | 2019-09-28 | 1 | -31/+46 |
| * | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-27 | 1 | -15/+13 |
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| | * | Resolve TODO with pin assignments for SRL* | Eddie Hung | 2019-09-04 | 1 | -4/+2 |
| | * | xilinx to use abc_map.v with -max_iter 1 | Eddie Hung | 2019-08-20 | 1 | -13/+13 |
| * | | Revert "Remove sequential extension" | Eddie Hung | 2019-08-20 | 1 | -0/+97 |
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| * | Remove sequential extension | Eddie Hung | 2019-08-20 | 1 | -97/+0 |
| * | LUTMUX -> LUTMUX6 | Eddie Hung | 2019-08-20 | 1 | -2/+2 |
| * | Remove delays from abc_map.v | Eddie Hung | 2019-08-20 | 1 | -5/+2 |
| * | Typo | Eddie Hung | 2019-08-20 | 1 | -1/+1 |
| * | Wrap SRL{16,32} too | Eddie Hung | 2019-08-20 | 1 | -0/+36 |
| * | Wrap LUTRAMs in order to capture comb/seq behaviour | Eddie Hung | 2019-08-20 | 1 | -0/+69 |
| * | Use abc_{map,unmap,model}.v | Eddie Hung | 2019-08-20 | 1 | -0/+120 |
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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