iCE40/yosys - clone of https://github.com/YosysHQ/yosys

	Commit message (Expand)	Author	Age	Files	Lines
*	machxo2: synth_machxo2 now maps ports to FACADE_IO.	William D. Jones	2021-02-23	2	-0/+12
*	machxo2: Add initial value for Q in FACADE_FF.	William D. Jones	2021-02-23	1	-0/+2
*	machxo2: Add FACADE_IO simulation model. More comments on models.	William D. Jones	2021-02-23	1	-0/+25
*	machxo2: Add FACADE_SLICE simulation model.	William D. Jones	2021-02-23	1	-0/+83
*	machxo2: Improve FACADE_FF simulation model.	William D. Jones	2021-02-23	1	-12/+20
*	machxo2: Improve LUT4 techmap. Use same output port name for LUT4 as Lattice.	William D. Jones	2021-02-23	2	-4/+4
*	machxo2: Add dff.ys test, fix another cells_map.v typo.	William D. Jones	2021-02-23	1	-1/+1
*	machxo2: Fix more oversights in machxo2 models. logic.ys test passes.	William D. Jones	2021-02-23	2	-2/+6
*	machxo2: Fix typos. test/arch/run-test.sh passes.	William D. Jones	2021-02-23	2	-2/+2
*	machxo2: Create basic techlibs and synth_machxo2 pass.	William D. Jones	2021-02-23	4	-0/+320