iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Fix files with CRLF line endings	Claire Xenia Wolf	2021-06-09	1	-31/+31
*	intel_alm: Fix illegal carry chains	gatecat	2021-05-15	2	-3/+5
*	intel_alm: Add global buffer insertion	gatecat	2021-05-15	5	-3/+67
*	intel_alm: Add IO buffer insertion	gatecat	2021-05-15	3	-0/+91
*	intel_alm: Add multiply signedness to cells	Dan Ravensloft	2020-08-26	4	-6/+99
*	intel_alm: fix typo in MISTRAL_MUL27X27 cell name	Dan Ravensloft	2020-08-13	1	-1/+1
*	intel_alm: add more megafunctions. NFC.	Dan Ravensloft	2020-08-12	1	-0/+431
*	intel_alm: direct M10K instantiation	Dan Ravensloft	2020-07-27	5	-35/+122
*	intel_alm: add additional ABC9 timings	Dan Ravensloft	2020-07-23	4	-72/+91
*	Revert "intel_alm: direct M10K instantiation"	Lofty	2020-07-13	5	-117/+34
*	intel_alm: direct M10K instantiation	Dan Ravensloft	2020-07-05	5	-34/+117
*	intel_alm: DSP inference	Dan Ravensloft	2020-07-05	4	-0/+135
*	synth_intel_alm: Use dfflegalize.	Marcelina Kościelnicka	2020-07-04	1	-117/+6
*	Improve MISTRAL_FF specify rules	Dan Ravensloft	2020-07-04	1	-5/+4
*	intel_alm: compose $__MISTRAL_FF_SYNCONLY from MISTRAL_FF	Eddie Hung	2020-07-04	2	-47/+2
*	intel_alm: add $__ prefix to MISTRAL_FF_SYNCONLY	Eddie Hung	2020-07-04	3	-3/+3
*	intel_alm: ABC9 sequential optimisations	Dan Ravensloft	2020-07-04	5	-10/+126
*	Add force_downto and force_upto wire attributes.	Marcelina Kościelnicka	2020-05-19	2	-0/+8
*	intel_alm: direct LUTRAM cell instantiation	Dan Ravensloft	2020-05-07	6	-50/+141
*	intel_alm: cleanup duplication	Dan Ravensloft	2020-04-24	1	-0/+63
*	intel_alm: Documentation improvements	Dan Ravensloft	2020-04-21	3	-14/+127
*	synth_intel_alm: VQM support	Dan Ravensloft	2020-04-15	1	-6/+2
*	synth_intel_alm: alternative synthesis for Intel FPGAs	Dan Ravensloft	2020-04-15	13	-0/+1082