iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Fix formatting for synth_intel.cc	Ben Widawsky	2019-05-09	1	-222/+211
*	Fixing issues in CycloneV cell sim	Diego	2019-04-11	1	-3/+9
*	Reduce amount of trailing whitespace in code base	Larry Doolittle	2019-02-28	2	-7/+7
*	Unify usage of noflatten among architectures	Miodrag Milanovic	2019-01-04	1	-2/+2
*	Fix typographical and grammatical errors and inconsistencies.	whitequark	2019-01-02	1	-1/+1
*	Changes in GoWin synth commands and ALU primitive support	Diego H	2018-12-03	1	-8/+8
*	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	1	-6/+6
*	Add "synth_intel --noiopads"	Clifford Wolf	2018-04-30	1	-2/+11
*	Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal val...	c60k28	2018-03-31	7	-60/+178
*	Add "dffinit -highlow" and fix synth_intel	Clifford Wolf	2018-01-09	1	-1/+1
*	Initial Cyclone 10 support	dh73	2017-11-08	5	-1/+308
*	Clean whitespace and permissions in techlibs/intel	Larry Doolittle	2017-10-05	21	-190/+190
*	Rename "write_verilog -nobasenradix" to "write_verilog -decimal"	Clifford Wolf	2017-10-03	1	-4/+1
*	Tested and working altsyncarm without init files	dh73	2017-10-01	2	-57/+59
*	Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and ...	dh73	2017-10-01	21	-0/+2721