| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth_intel: Remove incomplete Arria 10 GX support. | Marcelina Kościelnicka | 2020-08-21 | 1 | -1/+1 |
| * | intel: move Cyclone V support to intel_alm | Dan Ravensloft | 2020-08-20 | 1 | -1/+1 |
| * | intel: Use dfflegalize. | Marcelina Kościelnicka | 2020-07-13 | 1 | -0/+1 |
| * | synth_intel_alm: alternative synthesis for Intel FPGAs | Dan Ravensloft | 2020-04-15 | 1 | -1/+0 |
| * | synth_intel: a10gx -> arria10gx | Dan Ravensloft | 2019-12-10 | 1 | -1/+1 |
| * | synth_intel: cyclone10 -> cyclone10lp | Dan Ravensloft | 2019-12-10 | 1 | -1/+1 |
| * | techlibs/intel: Clean up Makefile | Ben Widawsky | 2019-08-05 | 1 | -15/+5 |
| * | intel: Map M9K BRAM only on families that have it | Dan Ravensloft | 2019-07-23 | 1 | -2/+2 |
| * | Initial Cyclone 10 support | dh73 | 2017-11-08 | 1 | -0/+2 |
| * | Clean whitespace and permissions in techlibs/intel | Larry Doolittle | 2017-10-05 | 1 | -0/+0 |
| * | Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and ... | dh73 | 2017-10-01 | 1 | -0/+22 |
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index : iCE40/yosys | |
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