iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	ice40: Add post-pnr ICESTORM_RAM model and fix FFs	David Shah	2019-10-23	1	-2/+340
*	ice40: Support for post-pnr timing simulation	David Shah	2019-10-23	1	-12/+96
*	Rename abc_* names/attributes to more precisely be abc9_*	Eddie Hung	2019-10-04	1	-79/+78
*	Panic over. Model was elsewhere. Re-arrange for consistency	Eddie Hung	2019-10-04	1	-28/+0
*	Comment out SB_MAC16 arrival time for now, need to handle all its modes	Eddie Hung	2019-08-28	1	-1/+1
*	Add arrival for SB_MAC16.O	Eddie Hung	2019-08-28	1	-0/+1
*	Add arrival times for U	Eddie Hung	2019-08-28	1	-0/+26
*	Round not floor	Eddie Hung	2019-08-28	1	-21/+21
*	Add LP timings	Eddie Hung	2019-08-28	1	-0/+26
*	LX -> LP	Eddie Hung	2019-08-28	1	-1/+1
*	Merge remote-tracking branch 'origin/eddie/fix_carry_wrapper' into xaig_arrival	Eddie Hung	2019-08-28	1	-1/+1
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\| *	Trailing comma	Eddie Hung	2019-08-28	1	-1/+1
* \|	Add arrival times for HX devices	Eddie Hung	2019-08-28	1	-21/+114
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*	Update to new $__ICE40_CARRY_WRAPPER	Eddie Hung	2019-08-28	1	-11/+8
*	Put abc_* attributes above port	Eddie Hung	2019-08-23	1	-2/+4
*	Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro	Eddie Hung	2019-08-19	1	-2/+2
*	Update abc_* attr in ecp5 and ice40	Eddie Hung	2019-08-16	1	-2/+8
*	ice40/cells_sim.v: Fix sign of J and K partial products	David Shah	2019-07-19	1	-5/+7
*	ice40/cells_sim.v: LSB of A/B only signed in 8x8 mode	David Shah	2019-07-19	1	-2/+2
*	$__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark	Eddie Hung	2019-07-15	1	-1/+1
*	Add new box to cells_sim.v	Eddie Hung	2019-07-12	1	-2/+25
*	Remove noise from ice40/cells_sim.v	Eddie Hung	2019-06-27	1	-5/+0
*	Refactor for one "abc_carry" attribute on module	Eddie Hung	2019-06-27	1	-2/+2
*	Fix and cleanup ice40 boxes for carry in/out	Eddie Hung	2019-06-22	1	-2/+2
*	Remove WIP ABC9 flop support	Eddie Hung	2019-06-14	1	-25/+25
*	Remove abc_flop{,_d} attributes from ice40/cells_sim.v	Eddie Hung	2019-06-12	1	-40/+20
*	Merge remote-tracking branch 'origin/master' into xc7mux	Eddie Hung	2019-06-10	1	-0/+24
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\| *	ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4k	Simon Schubert	2019-06-10	1	-0/+24
* \|	Make SB_LUT4 a whitebox, SB_DFF a blackbox (for now)	Eddie Hung	2019-06-03	1	-3/+3
* \|	Consistent with xilinx	Eddie Hung	2019-06-03	1	-1/+1
* \|	Merge branch 'xaig' into xc7mux	Eddie Hung	2019-05-31	1	-1/+1
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\| * \|	Use nonblocking	Eddie Hung	2019-04-23	1	-1/+1
* \| \|	Merge remote-tracking branch 'origin/master' into xc7mux	Eddie Hung	2019-05-21	1	-0/+11
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\| *	ice40/cells_sim.v: Add support for TRIM input to SB_HFOSC	Sylvain Munaut	2019-05-13	1	-0/+11
* \|	Merge remote-tracking branch 'origin/master' into xaig	Eddie Hung	2019-04-22	1	-10/+19
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\| *	ice40 cells_sim.v: SB_IO: update clock enable behaviour based on hardware exp...	Luke Wren	2019-04-21	1	-10/+19
* \|	Convert to use #945	Eddie Hung	2019-04-21	1	-8/+2
* \|	ABC_FLOPS -> ABC_MODEL -- only whitebox if ABC_MODEL set	Eddie Hung	2019-04-19	1	-3/+6
* \|	Fix SB_DFF comb model	Eddie Hung	2019-04-18	1	-1/+1
* \|	Missing close bracket	Eddie Hung	2019-04-18	1	-1/+1
* \|	Annotate SB_DFF* with abc_flop and abc_box_id	Eddie Hung	2019-04-18	1	-22/+49
* \|	Use new -wb flag for ABC flow	Eddie Hung	2019-04-18	1	-0/+2
* \|	Missing abc_flop_q attribute on SPRAM	Eddie Hung	2019-04-17	1	-1/+1
* \|	Mark seq output ports with "abc_flop_q" attr	Eddie Hung	2019-04-17	1	-24/+24
* \|	Revert "Try using an ICE40_CARRY_LUT primitive to avoid ABC issues"	Eddie Hung	2019-04-17	1	-22/+0
* \|	Try using an ICE40_CARRY_LUT primitive to avoid ABC issues	Eddie Hung	2019-04-17	1	-0/+22
* \|	Add ice40 box files	Eddie Hung	2019-04-16	1	-0/+1
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*	Remove ice40/cells_sim.v hack to avoid warning for blocking memory writes	Clifford Wolf	2019-03-12	1	-19/+0
*	ice40: Add ice40_braminit pass to allow initialization of BRAM from file	Sylvain Munaut	2019-03-08	1	-37/+51
*	Improve iCE40 SB_MAC16 model	Clifford Wolf	2019-02-20	1	-17/+10