iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Order ports with default assignments first	Sean Anderson	2022-08-09	1	-10/+38
*	Fixed Verific parser error in ice40 cell library	Claire Xenia Wolf	2021-10-19	1	-22/+62
*	ice40: Fix typo in SB_CARRY specify for LP/UltraPlus	Sylvain Munaut	2021-08-17	1	-2/+2
*	Fix icestorm links	Claire Xenia Wolf	2021-06-09	1	-495/+495
*	Add default assignments to other SB_* simulation models	Claire Xenia Wolf	2021-04-20	1	-24/+44
*	Add default assignments to SB_LUT4	Claire Xenia Wolf	2021-04-20	1	-1/+17
*	Fix Verilator sim warnings: 1 BLKSEQ and 3 WIDTH	Xark	2020-06-14	1	-7/+7
*	xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cells	Eddie Hung	2020-05-14	1	-0/+153
*	ice40: add synth_ice40 -dff option, support with -abc9	Eddie Hung	2020-05-14	1	-0/+13
*	ice40: fix ICESTORM_LC process sensitivity	Eddie Hung	2020-05-12	1	-1/+1
*	ice40: Fix typos in SPRAM ABC9 timing specs	Sylvain Munaut	2020-03-20	1	-2/+2
*	ice40: Fix SPRAM model to keep data stable if chipselect is low	Sylvain Munaut	2020-03-14	1	-5/+8
*	ice40: fix specify for ICE40_{LP,U}	Eddie Hung	2020-03-05	1	-4/+4
*	ice40: fix implicit signal in specify, also clamp negative times to 0	Eddie Hung	2020-03-04	1	-22/+22
*	ice40: add delays to SB_CARRY	Eddie Hung	2020-02-27	1	-0/+30
*	More +/ice40/cells_sim.v fixes	Eddie Hung	2020-02-27	1	-27/+27
*	ice40: fix specify for inverted clocks	Eddie Hung	2020-02-27	1	-27/+27
*	ice40: specify fixes	Eddie Hung	2020-02-27	1	-54/+54
*	ice40: move over to specify blocks for -abc9	Eddie Hung	2020-02-27	1	-85/+1283
*	ice40: add SB_SPRAM256KA arrival time	Eddie Hung	2020-01-24	1	-0/+1
*	ice40: Add post-pnr ICESTORM_RAM model and fix FFs	David Shah	2019-10-23	1	-2/+340
*	ice40: Support for post-pnr timing simulation	David Shah	2019-10-23	1	-12/+96
*	Rename abc_* names/attributes to more precisely be abc9_*	Eddie Hung	2019-10-04	1	-79/+78
*	Panic over. Model was elsewhere. Re-arrange for consistency	Eddie Hung	2019-10-04	1	-28/+0
*	Comment out SB_MAC16 arrival time for now, need to handle all its modes	Eddie Hung	2019-08-28	1	-1/+1
*	Add arrival for SB_MAC16.O	Eddie Hung	2019-08-28	1	-0/+1
*	Add arrival times for U	Eddie Hung	2019-08-28	1	-0/+26
*	Round not floor	Eddie Hung	2019-08-28	1	-21/+21
*	Add LP timings	Eddie Hung	2019-08-28	1	-0/+26
*	LX -> LP	Eddie Hung	2019-08-28	1	-1/+1
*	Merge remote-tracking branch 'origin/eddie/fix_carry_wrapper' into xaig_arrival	Eddie Hung	2019-08-28	1	-1/+1
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\| *	Trailing comma	Eddie Hung	2019-08-28	1	-1/+1
* \|	Add arrival times for HX devices	Eddie Hung	2019-08-28	1	-21/+114
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*	Update to new $__ICE40_CARRY_WRAPPER	Eddie Hung	2019-08-28	1	-11/+8
*	Put abc_* attributes above port	Eddie Hung	2019-08-23	1	-2/+4
*	Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro	Eddie Hung	2019-08-19	1	-2/+2
*	Update abc_* attr in ecp5 and ice40	Eddie Hung	2019-08-16	1	-2/+8
*	ice40/cells_sim.v: Fix sign of J and K partial products	David Shah	2019-07-19	1	-5/+7
*	ice40/cells_sim.v: LSB of A/B only signed in 8x8 mode	David Shah	2019-07-19	1	-2/+2
*	$__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark	Eddie Hung	2019-07-15	1	-1/+1
*	Add new box to cells_sim.v	Eddie Hung	2019-07-12	1	-2/+25
*	Remove noise from ice40/cells_sim.v	Eddie Hung	2019-06-27	1	-5/+0
*	Refactor for one "abc_carry" attribute on module	Eddie Hung	2019-06-27	1	-2/+2
*	Fix and cleanup ice40 boxes for carry in/out	Eddie Hung	2019-06-22	1	-2/+2
*	Remove WIP ABC9 flop support	Eddie Hung	2019-06-14	1	-25/+25
*	Remove abc_flop{,_d} attributes from ice40/cells_sim.v	Eddie Hung	2019-06-12	1	-40/+20
*	Merge remote-tracking branch 'origin/master' into xc7mux	Eddie Hung	2019-06-10	1	-0/+24
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\| *	ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4k	Simon Schubert	2019-06-10	1	-0/+24
* \|	Make SB_LUT4 a whitebox, SB_DFF a blackbox (for now)	Eddie Hung	2019-06-03	1	-3/+3
* \|	Consistent with xilinx	Eddie Hung	2019-06-03	1	-1/+1