aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs/ice40/cells_sim.v
Commit message (Expand)AuthorAgeFilesLines
* ice40: fix ICESTORM_LC process sensitivityEddie Hung2020-05-121-1/+1
* ice40: Fix typos in SPRAM ABC9 timing specsSylvain Munaut2020-03-201-2/+2
* ice40: Fix SPRAM model to keep data stable if chipselect is lowSylvain Munaut2020-03-141-5/+8
* ice40: fix specify for ICE40_{LP,U}Eddie Hung2020-03-051-4/+4
* ice40: fix implicit signal in specify, also clamp negative times to 0Eddie Hung2020-03-041-22/+22
* ice40: add delays to SB_CARRYEddie Hung2020-02-271-0/+30
* More +/ice40/cells_sim.v fixesEddie Hung2020-02-271-27/+27
* ice40: fix specify for inverted clocksEddie Hung2020-02-271-27/+27
* ice40: specify fixesEddie Hung2020-02-271-54/+54
* ice40: move over to specify blocks for -abc9Eddie Hung2020-02-271-85/+1283
* ice40: add SB_SPRAM256KA arrival timeEddie Hung2020-01-241-0/+1
* ice40: Add post-pnr ICESTORM_RAM model and fix FFsDavid Shah2019-10-231-2/+340
* ice40: Support for post-pnr timing simulationDavid Shah2019-10-231-12/+96
* Rename abc_* names/attributes to more precisely be abc9_*Eddie Hung2019-10-041-79/+78
* Panic over. Model was elsewhere. Re-arrange for consistencyEddie Hung2019-10-041-28/+0
* Comment out SB_MAC16 arrival time for now, need to handle all its modesEddie Hung2019-08-281-1/+1
* Add arrival for SB_MAC16.OEddie Hung2019-08-281-0/+1
* Add arrival times for UEddie Hung2019-08-281-0/+26
* Round not floorEddie Hung2019-08-281-21/+21
* Add LP timingsEddie Hung2019-08-281-0/+26
* LX -> LPEddie Hung2019-08-281-1/+1
* Merge remote-tracking branch 'origin/eddie/fix_carry_wrapper' into xaig_arrivalEddie Hung2019-08-281-1/+1
|\
| * Trailing commaEddie Hung2019-08-281-1/+1
* | Add arrival times for HX devicesEddie Hung2019-08-281-21/+114
|/
* Update to new $__ICE40_CARRY_WRAPPEREddie Hung2019-08-281-11/+8
* Put abc_* attributes above portEddie Hung2019-08-231-2/+4
* Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithroEddie Hung2019-08-191-2/+2
* Update abc_* attr in ecp5 and ice40Eddie Hung2019-08-161-2/+8
* ice40/cells_sim.v: Fix sign of J and K partial productsDavid Shah2019-07-191-5/+7
* ice40/cells_sim.v: LSB of A/B only signed in 8x8 modeDavid Shah2019-07-191-2/+2
* $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequarkEddie Hung2019-07-151-1/+1
* Add new box to cells_sim.vEddie Hung2019-07-121-2/+25
* Remove noise from ice40/cells_sim.vEddie Hung2019-06-271-5/+0
* Refactor for one "abc_carry" attribute on moduleEddie Hung2019-06-271-2/+2
* Fix and cleanup ice40 boxes for carry in/outEddie Hung2019-06-221-2/+2
* Remove WIP ABC9 flop supportEddie Hung2019-06-141-25/+25
* Remove abc_flop{,_d} attributes from ice40/cells_sim.vEddie Hung2019-06-121-40/+20
* Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-101-0/+24
|\
| * ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4kSimon Schubert2019-06-101-0/+24
* | Make SB_LUT4 a whitebox, SB_DFF a blackbox (for now)Eddie Hung2019-06-031-3/+3
* | Consistent with xilinxEddie Hung2019-06-031-1/+1
* | Merge branch 'xaig' into xc7muxEddie Hung2019-05-311-1/+1
|\ \
| * | Use nonblockingEddie Hung2019-04-231-1/+1
* | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-05-211-0/+11
|\ \ \ | |/ / |/| / | |/
| * ice40/cells_sim.v: Add support for TRIM input to SB_HFOSCSylvain Munaut2019-05-131-0/+11
* | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-221-10/+19
|\|
| * ice40 cells_sim.v: SB_IO: update clock enable behaviour based on hardware exp...Luke Wren2019-04-211-10/+19
* | Convert to use #945Eddie Hung2019-04-211-8/+2
* | ABC_FLOPS -> ABC_MODEL -- only whitebox if ABC_MODEL setEddie Hung2019-04-191-3/+6
* | Fix SB_DFF comb modelEddie Hung2019-04-181-1/+1