iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module	Larry Doolittle	2019-02-26	1	-22/+22
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*	Added RESET_TO_MAX parameter to $__COUNT_ cell. Cannot yet be extracted.	Andrew Zonenberg	2017-09-14	1	-2/+3
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*	Initial support for extraction of counters with clock enable	Andrew Zonenberg	2017-09-14	1	-21/+65
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*	extract_counter: Minor changes requested to comply with upstream policy, ↵	Andrew Zonenberg	2017-08-30	1	-3/+3
\| \| \| \|	fixed a few typos
*	Finished refactoring counter extraction to be nice and generic. Implemented ↵	Andrew Zonenberg	2017-08-28	1	-0/+68
\| \| \| \|	techmapping from $__COUNT_ to GP_COUNTx cells.
*	Initial implementation of techlib support for GreenPAK latches. ↵	Andrew Zonenberg	2016-12-05	1	-0/+52
\| \| \| \|	Instantiation only, no behavioral inference yet.
*	greenpak4: Changed name of inverted output ports for consistency	Andrew Zonenberg	2016-08-14	1	-4/+4
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*	greenpak4: Added GP_DFFxI cells	Andrew Zonenberg	2016-08-14	1	-0/+26
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*	Added tri-state I/O extraction for GreenPak	Andrew Zonenberg	2016-05-03	1	-0/+9
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*	Added GreenPak inverter support	Andrew Zonenberg	2016-04-01	1	-2/+7
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*	Fixed incorrect port name in cells_map.v	Andrew Zonenberg	2016-03-31	1	-2/+2
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*	Added GP_DFFS, GP_DFFR, and GP_DFFSR	Clifford Wolf	2016-03-23	1	-10/+16
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*	Renamed GreenPAK4 cells, improved GP4 DFF mapping	Clifford Wolf	2015-09-18	1	-5/+15
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*	Added GreenPAK4 skeleton	Clifford Wolf	2015-09-16	1	-0/+38