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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-03-31 22:51:22 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-03-31 22:51:22 -0700 |
| commit | 7498ff8041cdd464521a6802055a9893a0c6cf61 (patch) | |
| tree | 92be9876935ba4a555a9e0599c791c9d4745234f /techlibs/greenpak4/cells_map.v | |
| parent | c04a3d276320aa9aca4e3a678df3135b35473055 (diff) | |
| download | yosys-7498ff8041cdd464521a6802055a9893a0c6cf61.tar.gz yosys-7498ff8041cdd464521a6802055a9893a0c6cf61.tar.bz2 yosys-7498ff8041cdd464521a6802055a9893a0c6cf61.zip | |
Fixed incorrect port name in cells_map.v
Diffstat (limited to 'techlibs/greenpak4/cells_map.v')
| -rw-r--r-- | techlibs/greenpak4/cells_map.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/greenpak4/cells_map.v b/techlibs/greenpak4/cells_map.v index e24d24973..ce517d94b 100644 --- a/techlibs/greenpak4/cells_map.v +++ b/techlibs/greenpak4/cells_map.v @@ -5,7 +5,7 @@ module GP_DFFS(input D, CLK, nSET, output reg Q); .SRMODE(1'b1), ) _TECHMAP_REPLACE_ ( .D(D), - .CLK(C), + .CLK(CLK), .nSR(nSET), .Q(Q) ); @@ -18,7 +18,7 @@ module GP_DFFR(input D, CLK, nRST, output reg Q); .SRMODE(1'b0), ) _TECHMAP_REPLACE_ ( .D(D), - .CLK(C), + .CLK(CLK), .nSR(nRST), .Q(Q) ); |