iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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\| *	Updating gowin	Diego H	2019-09-02	2	-2/+2
* \|	gowin: add splitnets to appease the PnR	Pepijn de Vos	2019-09-04	1	-0/+1
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*	Fix formatting for msys2 mingw build using GetSize	Miodrag Milanovic	2019-08-01	1	-2/+2
*	Merge branch 'master' of https://github.com/dh73/yosys_gowin into dh73-master	Clifford Wolf	2019-04-22	10	-10/+458
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\| *	GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flow	Diego	2019-04-12	10	-11/+459
* \|	Make nobram false by default for gowin	Miodrag Milanovic	2019-04-02	1	-1/+1
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*	Reduce amount of trailing whitespace in code base	Larry Doolittle	2019-02-28	2	-7/+7
*	Unify usage of noflatten among architectures	Miodrag Milanovic	2019-01-04	1	-3/+11
*	Fix typographical and grammatical errors and inconsistencies.	whitequark	2019-01-02	1	-1/+1
*	Changes in GoWin synth commands and ALU primitive support	Diego H	2018-12-03	4	-4/+83
*	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	1	-4/+4
*	Indenting fixes in gowin sim cell lib	Clifford Wolf	2016-11-08	1	-20/+28
*	Added hex constant support to write_verilog	Clifford Wolf	2016-11-03	1	-1/+1
*	Added initial version of "synth_gowin"	Clifford Wolf	2016-11-01	4	-0/+266