iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	iopadmap: Add native support for negative-polarity output enable.	Marcelina Kościelnicka	2021-11-09	1	-8/+0
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*	Gowin: deal with active-low tristate (#2971)	Pepijn de Vos	2021-08-20	1	-0/+7
\| \| \| \| \| \| \| \| \|	* deal with active-low tristate * remove empty port * update sim models * add expected lut1 to tests
*	gowin: Use dfflegalize.	Marcelina Kościelnicka	2020-07-06	1	-145/+40
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*	Update dff2dffe, dff2dffs, zinit to new FF types.	Marcelina Kościelnicka	2020-06-23	1	-24/+24
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*	Add force_downto and force_upto wire attributes.	Marcelina Kościelnicka	2020-05-19	1	-0/+1
\| \| \| \|	Fixes #2058.
*	attempt to fix formatting	Pepijn de Vos	2019-11-25	1	-154/+154
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*	gowin: add and test dff init values	Pepijn de Vos	2019-11-25	1	-38/+187
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*	Remove dff init altogether	Pepijn de Vos	2019-11-19	1	-2/+3
\| \| \| \| \|	The hardware does not actually support it. In reality it is always initialised to its reset value.
*	fix fsm test with proper clock enable polarity	Pepijn de Vos	2019-11-11	1	-4/+4
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*	fix wide luts	Pepijn de Vos	2019-11-06	1	-12/+12
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*	add wide luts	Pepijn de Vos	2019-10-28	1	-0/+24
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*	add a few more missing dff	Pepijn de Vos	2019-10-21	1	-7/+16
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*	add negedge DFF	Pepijn de Vos	2019-10-21	1	-7/+26
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*	Revert "add MUX support"	Pepijn de Vos	2019-09-06	1	-3/+0
\| \| \| \| \| \|	It turns out that they make everything worse and they don't PnR. This reverts commit 3eff2271d0fe25632f7e6b22cf0be078d2cd9990.
*	add more DFF to sim lib	Pepijn de Vos	2019-09-06	1	-6/+6
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*	WIP aditional DFF primitives	Pepijn de Vos	2019-09-05	1	-1/+46
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*	add MUX support	Pepijn de Vos	2019-09-05	1	-0/+3
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*	GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flow	Diego	2019-04-12	1	-1/+5
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*	Added initial version of "synth_gowin"	Clifford Wolf	2016-11-01	1	-0/+31