| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | gatemate: Fix minor issues with `memory_libmap` (#3343) | Patrick Urban | 2022-05-27 | 1 | -28/+35 |
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| * | gatemate: Use `memory_libmap` pass. | Marcelina Kościelnicka | 2022-05-18 | 1 | -495/+850 |
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| * | synth_gatemate Revert cascade A/B port mixup | Patrick Urban | 2021-11-13 | 1 | -4/+4 |
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| * | synth_gatemate: Add block RAM cascade support | Patrick Urban | 2021-11-13 | 1 | -23/+11 |
| | | | | | | * add simulation model for block RAM cascade in 40K mode * limit 20K_SDP and 40K_SDP to 40 and 80 bits (the only useful configurations) | ||||
| * | synth_gatemate: Revise block RAM read modes and initialization | Patrick Urban | 2021-11-13 | 1 | -29/+22 |
| | | | | | | | | | * enable mixed read-width / write-width ports in SDP mode * fix NO_CHANGE and WRITE_THROUGH behavior during read access * remove redundant zero-initialization * set A/B_WE bit during map (gatemate_bramopt pass could be removed later) * differentiate "upper" and "lower" initialization for cascade mode | ||||
| * | synth_gatemate: Initial implementation | Patrick Urban | 2021-11-13 | 1 | -0/+539 |
| Signed-off-by: Patrick Urban <patrick.urban@web.de> | |||||
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index : iCE40/yosys | |
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