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| author | Patrick Urban <patrick.urban@web.de> | 2021-11-10 16:18:13 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-11-13 21:53:25 +0100 |
| commit | 0d871b6c49b326315436fd8cdbd50b8d90a2990f (patch) | |
| tree | 74c5f86eebfcee99f1485027d5092cfb16a2b60d /techlibs/gatemate/brams_map.v | |
| parent | 285ec0547b19a48c6b52050ee715940f1635994a (diff) | |
| download | yosys-0d871b6c49b326315436fd8cdbd50b8d90a2990f.tar.gz yosys-0d871b6c49b326315436fd8cdbd50b8d90a2990f.tar.bz2 yosys-0d871b6c49b326315436fd8cdbd50b8d90a2990f.zip | |
synth_gatemate: Add block RAM cascade support
* add simulation model for block RAM cascade in 40K mode
* limit 20K_SDP and 40K_SDP to 40 and 80 bits (the only useful configurations)
Diffstat (limited to 'techlibs/gatemate/brams_map.v')
| -rw-r--r-- | techlibs/gatemate/brams_map.v | 34 |
1 files changed, 11 insertions, 23 deletions
diff --git a/techlibs/gatemate/brams_map.v b/techlibs/gatemate/brams_map.v index b7f0ff73e..2e5e1a5cc 100644 --- a/techlibs/gatemate/brams_map.v +++ b/techlibs/gatemate/brams_map.v @@ -50,19 +50,13 @@ module \$__CC_BRAM_20K_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1 wire [15:0] ADDRA = {A1ADDR, 7'b0};
wire [15:0] ADDRB = {B1ADDR, 7'b0};
- localparam INIT_CHUNK_SIZE = (CFG_DBITS <= 2) ? 256 : 320;
+ localparam INIT_CHUNK_SIZE = 320;
function [319:0] permute_init;
input [INIT_CHUNK_SIZE-1:0] chunk;
integer i;
begin
- if (CFG_DBITS <= 2) begin
- for (i = 0; i < 64; i = i + 1) begin
- permute_init[i * 5 +: 5] = {1'b0, chunk[i * 4 +: 4]};
- end
- end else begin
- permute_init = chunk;
- end
+ permute_init = chunk;
end
endfunction
@@ -133,19 +127,13 @@ module \$__CC_BRAM_40K_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1 wire [15:0] ADDRA = {A1ADDR, 7'b0};
wire [15:0] ADDRB = {B1ADDR, 7'b0};
- localparam INIT_CHUNK_SIZE = (CFG_DBITS <= 2) ? 256 : 320;
+ localparam INIT_CHUNK_SIZE = 320;
function [319:0] permute_init;
input [INIT_CHUNK_SIZE-1:0] chunk;
integer i;
begin
- if (CFG_DBITS <= 2) begin
- for (i = 0; i < 64; i = i + 1) begin
- permute_init[i * 5 +: 5] = {1'b0, chunk[i * 4 +: 4]};
- end
- end else begin
- permute_init = chunk;
- end
+ permute_init = chunk;
end
endfunction
@@ -173,7 +161,7 @@ module \$__CC_BRAM_40K_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1 .B_ECC_2B_ERR(B_ECC_2B_ERR),
.A_CLK(CLK2),
.B_CLK(CLK3),
- .A_EN(|A1EN),
+ .A_EN(1'b1),
.B_EN(B1EN),
.A_WE(|A1EN),
.B_WE(1'b0),
@@ -440,7 +428,7 @@ module \$__CC_BRAM_CASCADE (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1 wire A_CAS, B_CAS;
// unconnected signals
- wire [39:0] A_UP_DO, A_LO_DO, B_LO_DO;
+ wire [39:0] A_UP_DO;
wire A_ECC_1B_ERR, B_ECC_1B_ERR, A_ECC_2B_ERR, B_ECC_2B_ERR;
localparam INIT_CHUNK_SIZE = 256;
@@ -462,7 +450,7 @@ module \$__CC_BRAM_CASCADE (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1 `undef INIT_UPPER
.LOC("UNPLACED"),
.CAS("UPPER"),
- .A_RD_WIDTH(0), .B_RD_WIDTH(CFG_DBITS),
+ .A_RD_WIDTH(CFG_DBITS), .B_RD_WIDTH(0),
.A_WR_WIDTH(CFG_DBITS), .B_WR_WIDTH(0),
.RAM_MODE("TDP"),
.A_WR_MODE("NO_CHANGE"), .B_WR_MODE("NO_CHANGE"),
@@ -474,8 +462,8 @@ module \$__CC_BRAM_CASCADE (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1 ) upper_cell (
.A_CI(A_CAS),
.B_CI(B_CAS),
- .A_DO(A_UP_DO),
- .B_DO(B1DATA),
+ .A_DO(B1DATA),
+ .B_DO(A_UP_DO),
.A_ECC_1B_ERR(A_ECC_1B_ERR),
.B_ECC_1B_ERR(B_ECC_1B_ERR),
.A_ECC_2B_ERR(A_ECC_2B_ERR),
@@ -500,7 +488,7 @@ module \$__CC_BRAM_CASCADE (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1 `undef INIT_LOWER
.LOC("UNPLACED"),
.CAS("LOWER"),
- .A_RD_WIDTH(0), .B_RD_WIDTH(CFG_DBITS),
+ .A_RD_WIDTH(CFG_DBITS), .B_RD_WIDTH(0),
.A_WR_WIDTH(CFG_DBITS), .B_WR_WIDTH(0),
.RAM_MODE("TDP"),
.A_WR_MODE("NO_CHANGE"), .B_WR_MODE("NO_CHANGE"),
@@ -510,7 +498,7 @@ module \$__CC_BRAM_CASCADE (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1 .A_DO_REG(1'b0), .B_DO_REG(1'b0),
.A_ECC_EN(1'b0), .B_ECC_EN(1'b0)
) lower_cell (
- .A_CI(1'b1),
+ .A_CI(),
.B_CI(),
.A_CO(A_CAS),
.B_CO(B_CAS),
|