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* FF should be initialized to 0Miodrag Milanovic2019-10-041-1/+3
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* Add missing latch mappingMiodrag Milanovic2019-10-041-0/+12
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* better handling of lut and begin/end addMiodrag Milanovic2019-09-181-4/+10
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* Added simulation models for Efinix and AnlogicMiodrag Milanovic2019-09-151-2/+62
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* Fix missing newline at end of fileClifford Wolf2019-08-221-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix formatingMiodrag Milanovic2019-08-111-2/+2
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* one bit enable signalMiodrag Milanovic2019-08-111-1/+1
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* fix mixing signals on FF mappingMiodrag Milanovic2019-08-111-4/+4
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* Replaced custom step with setundefMiodrag Milanovic2019-08-113-91/+1
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* Fixed data widthMiodrag Milanovic2019-08-111-2/+2
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* Adding new pass to fix carry chainMiodrag Milanovic2019-08-113-0/+124
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* cleanupMiodrag Milanovic2019-08-111-4/+7
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* Fix COMiodrag Milanovic2019-08-091-26/+24
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* clock for ram trough gbufMiodrag Milanovic2019-08-041-0/+6
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* Added bram supportMiodrag Milanovic2019-08-046-1/+260
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* Custom step to add global clock buffersMiodrag Milanovic2019-08-034-1/+129
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* Initial EFINIX supportMiodrag Milanovic2019-08-035-0/+370
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