| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Harmonize BRAM/LUTRAM descriptions across all of Yosys. | whitequark | 2020-01-01 | 1 | -1/+1 |
| * | Fix missing newline at end of file | Clifford Wolf | 2019-08-22 | 1 | -1/+1 |
| * | Replaced custom step with setundef | Miodrag Milanovic | 2019-08-11 | 1 | -1/+0 |
| * | Adding new pass to fix carry chain | Miodrag Milanovic | 2019-08-11 | 1 | -0/+1 |
| * | Added bram support | Miodrag Milanovic | 2019-08-04 | 1 | -0/+3 |
| * | Custom step to add global clock buffers | Miodrag Milanovic | 2019-08-03 | 1 | -0/+1 |
| * | Initial EFINIX support | Miodrag Milanovic | 2019-08-03 | 1 | -0/+6 |
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index : iCE40/yosys | |
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