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| * | Put abc_* attributes above portEddie Hung2019-08-231-5/+10
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| * Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithroEddie Hung2019-08-191-2/+2
| * Update abc_* attr in ecp5 and ice40Eddie Hung2019-08-161-9/+13
* | ecp5: Replace '-dsp' with inverse logic '-nodsp' to match synth_xilinxDavid Shah2019-08-081-11/+11
* | ecp5: Bring up to date with mul2dsp changesDavid Shah2019-08-082-2/+10
* | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-071-101/+244
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| * ecp5: Make cells_sim.v consistent with nextpnrDavid Shah2019-08-071-101/+244
* | Merge remote-tracking branch 'origin/master' into ice40dspEddie Hung2019-07-184-15/+19
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| * synth_ecp5: rename dram to lutram everywhere.whitequark2019-07-164-13/+13
| * synth_{ice40,ecp5}: more sensible pass label naming.whitequark2019-07-161-3/+7
* | OUT port to Y in generic DSPEddie Hung2019-07-151-2/+2
* | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-07-101-1/+4
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| * Error out if -abc9 and -retime specifiedEddie Hung2019-07-101-0/+3
| * synth_ecp5: Fix typo in copyright headerDavid Shah2019-07-091-1/+1
* | xc7: Map combinational DSP48E1sDavid Shah2019-07-081-2/+2
* | Add mul2dsp multiplier splitting rule and ECP5 mappingDavid Shah2019-07-083-2/+42
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* install *_nowide.lut filesEddie Hung2019-06-291-0/+1
* Disable boxing of ECP5 dist RAM due to regressionEddie Hung2019-06-281-1/+1
* Add write address to abc_scc_break of ECP5 dist RAMEddie Hung2019-06-281-1/+1
* Fix DO4 typoEddie Hung2019-06-281-1/+1
* Refactor for one "abc_carry" attribute on moduleEddie Hung2019-06-271-5/+3
* Merge origin/masterEddie Hung2019-06-272-43/+91
* Add WE to ECP5 dist RAM's abc_scc_break tooEddie Hung2019-06-261-1/+1
* Update comment on boxesEddie Hung2019-06-261-2/+3
* Add _nowide variants of LUT libraries in -nowidelut flowsEddie Hung2019-06-262-1/+16
* Merge branch 'koriakin/xc7nocarrymux' into xaigEddie Hung2019-06-261-7/+6
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| * synth_ecp5 rename -nomux to -nowidelut, but preserve formerEddie Hung2019-06-261-6/+6
* | Re-enable dist RAM boxes for ECP5Eddie Hung2019-06-241-1/+1
* | Revert "Re-enable dist RAM boxes for ECP5"Eddie Hung2019-06-241-1/+1
* | Re-enable dist RAM boxes for ECP5Eddie Hung2019-06-241-1/+1
* | Add comments to ecp5 boxEddie Hung2019-06-221-0/+6
* | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-211-4/+5
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| * ecp5: Improve mapping of $alu when BI is usedDavid Shah2019-06-211-4/+5
* | Clean upEddie Hung2019-06-181-6/+4
* | Comment out dist RAM boxing on ECP5 for nowEddie Hung2019-06-141-1/+1
* | Remove WIP ABC9 flop supportEddie Hung2019-06-141-3/+3
* | ecp5: Add abc9 optionDavid Shah2019-06-146-70/+184
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* ECP5: implement all Diamond I/O buffer primitives.whitequark2019-06-061-0/+15
* Add handling of init attributes in "opt_expr -undriven"Clifford Wolf2019-04-301-1/+1
* ecp5: Demote conflicting FF init values to a warningDavid Shah2019-03-041-2/+7
* Fix ECP5 cells_sim for iverilogMiodrag Milanovic2019-03-011-2/+3
* Merge pull request #794 from daveshah1/ecp5improveClifford Wolf2019-02-287-12/+388
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| * ecp5: Compatibility with Migen AsyncResetSynchronizerDavid Shah2019-02-252-0/+20
| * ecp5: Add DDRDLLADavid Shah2019-02-191-0/+9
| * ecp5: Add DELAYF/DELAYG blackboxesDavid Shah2019-02-191-0/+18
| * ecp5: Add ECLKSYNCB blackboxDavid Shah2019-02-131-1/+7
| * ecp5: Full set of IO-related blackboxesDavid Shah2019-02-121-0/+102
| * ecp5: Support for flipflop initialisationDavid Shah2019-01-223-4/+199
| * ecp5: Add LSRMODE to flipflops for PRLD supportDavid Shah2019-01-211-7/+16
| * ecp5: More blackboxesDavid Shah2019-01-211-0/+17
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