| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | coolrunner2: Add INVERT parameter to some BUFGs | Robert Ou | 2017-08-14 | 1 | -2/+6 |
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| * | coolrunner2: Add FFs with clock enable to cells_sim.v | Robert Ou | 2017-08-14 | 1 | -0/+60 |
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| * | coolrunner2: Add a few more primitives | Robert Ou | 2017-06-25 | 1 | -0/+110 |
| | | | | | These cannot be inferred yet, but add them to cells_sim.v for now | ||||
| * | coolrunner2: Initial mapping of latches | Robert Ou | 2017-06-25 | 1 | -0/+40 |
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| * | coolrunner2: Initial mapping of DFFs | Robert Ou | 2017-06-25 | 1 | -0/+40 |
| | | | | | | All DFFs map to either FDCP (matches Xilinx) or a custom FDCP_N (negative-edge triggered) | ||||
| * | coolrunner2: Remove redundant INVERT_PTC | Robert Ou | 2017-06-25 | 1 | -2/+1 |
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| * | coolrunner2: Also construct the XOR cell in the macrocell | Robert Ou | 2017-06-25 | 1 | -0/+14 |
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| * | coolrunner2: Initial techmapping for $sop | Robert Ou | 2017-06-25 | 1 | -7/+9 |
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| * | coolrunner2: Initial commit | Robert Ou | 2017-06-24 | 1 | -0/+41 |
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index : iCE40/yosys | |
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