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* Add bitwise `$bweqx` and `$bwmux` cellsJannis Harder2022-11-302-1/+38
| | | | | | The new bitwise case equality (`$bweqx`) and bitwise mux (`$bwmux`) cells enable compact encoding and decoding of 3-valued logic signals using multiple 2-valued signals.
* simlib: Use optional SIMLIB_GLOBAL_CLOCK to define a global clock signalJannis Harder2022-11-301-2/+8
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* simlib: Silence iverilog warning for `$lut`Jannis Harder2022-11-301-1/+1
| | | | | | iverilog complains about implicitly truncating LUT when connecting it to the `$bmux` A input. This explicitly truncates it to avoid that warning without changing the behaviour otherwise.
* simlib: Fix wide $bmux and avoid iverilog warningsJannis Harder2022-11-301-2/+2
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* satgen, simlib: Consistent x-propagation for `$pmux` cellsJannis Harder2022-11-301-4/+11
| | | | | This updates satgen and simlib to use a `$pmux` model where the output is fully X when the S input is not all zero or one-hot with no x bits.
* simlib: Simplify recently changed $mux modelJannis Harder2022-10-281-4/+2
| | | | | | The use of a procedural continuous assignment introduced in #3526 was unintended and is completely unnecessary for the actual change of that PR.
* Merge pull request #3526 from jix/mux-simlib-evalJannis Harder2022-10-241-4/+1
|\ | | | | Consistent $mux undef handling
| * Consistent $mux undef handlingJannis Harder2022-10-241-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Change simlib's $mux cell to use the ternary operator as $_MUX_ already does * Stop opt_expr -keepdc from changing S=x to S=0 * Change const eval of $mux and $pmux to match the updated simlib (fixes sim) * The sat behavior of $mux already matches the updated simlib The verilog frontend uses $mux for the ternary operators and this changes all interpreations of the $mux cell (that I found) to match the verilog simulation behavior for the ternary operator. For 'if' and 'case' expressions the frontend may also use $mux but uses $eqx if the verilog simulation behavior is requested with the '-ifx' option. For $pmux there is a remaining mismatch between the sat behavior and the simlib behavior. Resolving this requires more discussion, as the $pmux cell does not directly correspond to a specific verilog construct.
* | Add smtmap.v describing the smt2 backend's behavior for undef bitsJannis Harder2022-10-202-0/+29
|/ | | | | | | | | Some builtin cells have an undefined (x) output even when all inputs are defined. This is not natively supported by the formal backends which will produce a fully defined value instead. This can lead to issues when combining different backends in a formal flow. To work around these, this adds a file containing verilog implementation of cells matching the fully defined behavior implemented by the smt2 backend.
* Add the $anyinit cell and the formalff passJannis Harder2022-08-161-0/+17
| | | | | | | These can be used to protect undefined flip-flop initialization values from optimizations that are not sound for formal verification and can help mapping all solver-provided values in witness traces for flows that use different backends simultaneously.
* Add -no-rw-check option to memory_dff + memory + synth_{ice40,ecp5,gowin}.Marcelina Kościelnicka2022-06-021-0/+9
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* Add $bmux and $demux cells.Marcelina Kościelnicka2022-01-282-24/+87
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* Hook up $aldff support in various passes.Marcelina Kościelnicka2021-10-021-1/+1
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* Add $aldff and $aldffe: flip-flops with async load.Marcelina Kościelnicka2021-10-023-0/+382
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* Add v2 memory cells.Marcelina Kościelnicka2021-08-111-0/+169
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* memory: Introduce $meminit_v2 cell, with EN input.Marcelina Kościelnicka2021-07-281-0/+24
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* Fix files with CRLF line endingsClaire Xenia Wolf2021-06-091-318/+318
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* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-086-7/+7
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* abc9: fix SCC issues (#2694)Eddie Hung2021-03-292-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * xilinx: add SCC test for DSP48E1 * xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1 Have a test that checks it works through ABC9 when enabled * abc9 to break SCCs using $__ABC9_SCC_BREAKER module * Add test * abc9_ops: remove refs to (* abc9_keep *) on wires * abc9_ops: do not bypass cells in an SCC * Add myself to CODEOWNERS for abc9* * Fix compile * abc9_ops: run -prep_hier before scc * Fix tests * Remove bug reference pending fix * abc9: fix for -prep_hier -dff * xaiger: restore PI handling * abc9_ops: -prep_xaiger sigmap * abc9_ops: -mark_scc -> -break_scc * abc9: eliminate hard-coded abc9.box from tests Also tidy up * Address review
* memory_dff: Remove now-useless write port handling.Marcelina Kościelnicka2021-03-081-6/+7
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* Fix syntax error in adff2dff.vMarcelina Kościelnicka2021-02-241-1/+1
| | | | Fixes #2600.
* verilog: significant block scoping improvementsZachary Snow2021-01-313-46/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
* Fix some trivial typos.Tom Verbeure2021-01-031-5/+5
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* Merge pull request #2347 from YosysHQ/mwk/techmap-shift-fixesclairexen2020-08-201-67/+35
|\ | | | | techmap/shift_shiftx: Remove the "shiftx2mux" special path.
| * techmap/shift_shiftx: Remove the "shiftx2mux" special path.Marcelina Kościelnicka2020-08-201-67/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Our techmap rules for $shift and $shiftx cells contained a special path that aimed to decompose the shift LSB-first instead of MSB-first in select cases that come up in pmux lowering. This path was needlessly overcomplicated and contained bugs. Instead of doing that, just switch over the main path to iterate LSB-first (except for the specially-handled MSB for signed shifts and overflow handling). This also makes the code consistent with shl/shr/sshl/sshr cells, which are already decomposed LSB-first. Fixes #2346.
* | Merge pull request #2319 from YosysHQ/mwk/techmap-celltype-patternclairexen2020-08-201-1/+1
|\ \ | |/ |/| techmap: Add support for [] wildcards in techmap_celltype.
| * techmap: Add support for [] wildcards in techmap_celltype.Marcelina Kościelnicka2020-08-021-1/+1
| | | | | | | | Fixes #1826.
* | Respect \A_SIGNED for $shiftXiretza2020-08-182-6/+16
| | | | | | | | | | | | This reflects the behaviour of $shr/$shl, which sign-extend their A operands to the size of their output, then do a logical shift (shift in 0-bits).
* | Replace opt_rmdff with opt_dff.Marcelina Kościelnicka2020-08-071-3/+3
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* simcells: Fix reset polarity for $_DLATCH_???_ cells.Marcelina Kościelnicka2020-06-302-5/+5
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* Add new FF types to simplemap.Marcelina Kościelnicka2020-06-231-1/+1
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* Add new builtin FF typesMarcelina Kościelnicka2020-06-233-0/+2293
| | | | | | | | | | | | | | The new types include: - FFs with async reset and enable (`$adffe`, `$_DFFE_[NP][NP][01][NP]_`) - FFs with sync reset (`$sdff`, `$_SDFF_[NP][NP][01]_`) - FFs with sync reset and enable, reset priority (`$sdffs`, `$_SDFFE_[NP][NP][01][NP]_`) - FFs with sync reset and enable, enable priority (`$sdffce`, `$_SDFFCE_[NP][NP][01][NP]_`) - FFs with async reset, set, and enable (`$dffsre`, `$_DFFSRE_[NP][NP][NP][NP]_`) - latches with reset or set (`$adlatch`, `$_DLATCH_[NP][NP][01]_`) The new FF types are not actually used anywhere yet (this is left for future commits).
* Use C++11 final/override keywords.whitequark2020-06-182-8/+8
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* Do not optimize away FFs in "prep" and Verific fron-endClaire Wolf2020-06-091-2/+2
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improveEddie Hung2020-06-041-1/+1
|\ | | | | abc9: -dff improvements
| * abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_Eddie Hung2020-05-291-1/+1
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* | Add flooring division operatorXiretza2020-05-282-0/+71
| | | | | | | | | | | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $divfloor cell provides this flooring division. This commit also fixes the handling of $div in opt_expr, which was previously optimized as if it was $divfloor.
* | Add flooring modulo operatorXiretza2020-05-282-3/+124
|/ | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $modfloor cell provides this flooring modulo (also known as "remainder" in several languages, but this name is ambiguous). This commit also fixes the handling of $mod in opt_expr, which was previously optimized as if it was $modfloor.
* Add force_downto and force_upto wire attributes.Marcelina Kościelnicka2020-05-196-23/+88
| | | | Fixes #2058.
* abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_Eddie Hung2020-05-142-14/+2
| | | | instead of moving them to $__ prefix
* abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove itEddie Hung2020-05-142-5/+4
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* abc9_ops/xaiger: further reducing Module::derive() calls by ...Eddie Hung2020-05-142-7/+5
| | | | replacing _all_ (* abc9_box *) instantiations with their derived types
* Cleanup; reduce Module::derive() callsEddie Hung2020-05-142-4/+4
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* abc9: only do +/abc9_map if `DFFEddie Hung2020-05-141-0/+2
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* abc9: not enough to techmap_fail on (* init=1 *), hide them using $__Eddie Hung2020-05-142-10/+26
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* abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ tooEddie Hung2020-05-144-0/+55
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* abc9_ops: add 'dff' label for auto handling of (* abc9_flop *) boxesEddie Hung2020-05-141-3/+0
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* techlibs/common: more robustness when *_WIDTH = 0Eddie Hung2020-05-052-7/+30
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* Fix the truth table for $_SR_* cells.Marcelina Kościelnicka2020-04-153-26/+21
| | | | | | | | This brings the documented behavior for these cells in line with $_DFFSR_* and $_DLATCHSR_*, which is that R has priority over S. The models were already reflecting that behavior. Also get rid of sim-synth mismatch in the models while we're at it.
* Merge pull request #1648 from YosysHQ/eddie/cmp2lcuEddie Hung2020-04-034-11/+120
|\ | | | | "techmap -map +/cmp2lcu.v" for decomposing arithmetic compares to $lcu
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