iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	RIP $safe_pmux	Clifford Wolf	2014-08-14	1	-27/+4
*	Bugfix in simlib.v for iverilog	Clifford Wolf	2014-07-29	1	-5/+6
*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29	1	-0/+48
*	Fixed simlib.v model for $mem	Clifford Wolf	2014-07-17	1	-15/+15
*	Updated simlib to new $mem/$memwr interface	Clifford Wolf	2014-07-16	1	-30/+55
*	Added SIMLIB_NOLUT to simlib.v	Clifford Wolf	2014-04-02	1	-0/+2
*	Added SIMLIB_NOSR to simlib.v	Clifford Wolf	2014-04-02	1	-0/+6
*	Added support for dlatchsr cells	Clifford Wolf	2014-03-31	1	-0/+32
*	Added $slice and $concat cell types	Clifford Wolf	2014-02-07	1	-0/+30
*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03	1	-13/+47
*	More changes to techlibs/common/simlib.v for LEC	Clifford Wolf	2014-01-31	1	-6/+11
*	Major rewrite of techlibs/common/simlib.v for LEC (cadance conformal)	Clifford Wolf	2014-01-29	1	-105/+305
*	Added $assert cell	Clifford Wolf	2014-01-19	1	-0/+15
*	Fixed $lut simlib model for a wider range of tools	Clifford Wolf	2014-01-18	1	-10/+12
*	More changes to simlib to make it friendlier to a wider range of tools	Clifford Wolf	2014-01-18	1	-10/+14
*	Fixed a type in $mem model in simlib.v	Clifford Wolf	2014-01-18	1	-1/+1
*	Added $bu0 cell to simlib.v	Clifford Wolf	2014-01-18	1	-0/+22
*	Added support for non-const === and !== (for miter circuits)	Clifford Wolf	2013-12-27	1	-0/+36
*	Renamed stdcells_sim.v to simcells.v and fixed blackbox.v	Clifford Wolf	2013-11-24	1	-8/+8
*	Cleanups and bugfixes in response to new internal cell checker	Clifford Wolf	2013-11-11	1	-6/+7
*	Added $sr, $dffsr and $dlatch cell types	Clifford Wolf	2013-10-18	1	-20/+76
*	Moved common techlib files to techlibs/common	Clifford Wolf	2013-09-15	1	-0/+944