iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
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*	Smaller default parameters in $mem simlib model	Clifford Wolf	2015-02-15	1	-2/+2
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*	Added $meminit support to "memory" command	Clifford Wolf	2015-02-14	1	-3/+15
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*	Added $meminit cell type	Clifford Wolf	2015-02-14	1	-0/+22
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*	Some test related fixes	Clifford Wolf	2015-02-12	1	-4/+4
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*	Added $equiv cell type	Clifford Wolf	2015-01-19	1	-1/+23
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*	Progress in memory_bram	Clifford Wolf	2015-01-03	1	-0/+3
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*	Added proper clkpol support to memory_bram	Clifford Wolf	2015-01-02	1	-1/+1
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*	New $mem simlib model	Clifford Wolf	2015-01-02	1	-95/+36
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*	Fixed simlib entries for $memrd and $memwr	Clifford Wolf	2014-12-30	1	-0/+2
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*	Added $dffe cell type	Clifford Wolf	2014-12-08	1	-0/+19
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*	Fixed $macc simlib model for zero-config	Clifford Wolf	2014-09-16	1	-1/+1
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*	Fixed simlib $macc model for xilinx xsim	Clifford Wolf	2014-09-08	1	-1/+15
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*	Simplified $fa undef model	Clifford Wolf	2014-09-08	1	-1/+1
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*	Fixes and cleanups for blackbox.v	Clifford Wolf	2014-09-08	1	-68/+70
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*	Added $lcu cell type	Clifford Wolf	2014-09-08	1	-0/+23
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*	Added "$fa" cell type	Clifford Wolf	2014-09-08	1	-0/+16
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*	Various bug fixes (related to $macc model testing)	Clifford Wolf	2014-09-06	1	-1/+1
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*	Added $macc SAT model	Clifford Wolf	2014-09-06	1	-3/+3
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*	Added $macc simlib model (also use as techmap rule for now)	Clifford Wolf	2014-09-06	1	-0/+86
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*	Removed $bu0 cell type	Clifford Wolf	2014-09-04	1	-24/+0
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*	Undef-related fixes in simlib $alu model	Clifford Wolf	2014-09-02	1	-3/+6
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*	Small bug fixes in $not, $neg, and $shiftx models	Clifford Wolf	2014-09-02	1	-3/+2
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*	Fixed "test_cell -simlib all"	Clifford Wolf	2014-09-01	1	-2/+3
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*	Added $alu cell type	Clifford Wolf	2014-08-30	1	-0/+45
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*	Renamed $lut ports to follow A-Y naming scheme	Clifford Wolf	2014-08-15	1	-11/+11
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*	RIP $safe_pmux	Clifford Wolf	2014-08-14	1	-27/+4
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*	Bugfix in simlib.v for iverilog	Clifford Wolf	2014-07-29	1	-5/+6
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*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29	1	-0/+48
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*	Fixed simlib.v model for $mem	Clifford Wolf	2014-07-17	1	-15/+15
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*	Updated simlib to new $mem/$memwr interface	Clifford Wolf	2014-07-16	1	-30/+55
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*	Added SIMLIB_NOLUT to simlib.v	Clifford Wolf	2014-04-02	1	-0/+2
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*	Added SIMLIB_NOSR to simlib.v	Clifford Wolf	2014-04-02	1	-0/+6
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*	Added support for dlatchsr cells	Clifford Wolf	2014-03-31	1	-0/+32
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*	Added $slice and $concat cell types	Clifford Wolf	2014-02-07	1	-0/+30
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*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03	1	-13/+47
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*	More changes to techlibs/common/simlib.v for LEC	Clifford Wolf	2014-01-31	1	-6/+11
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*	Major rewrite of techlibs/common/simlib.v for LEC (cadance conformal)	Clifford Wolf	2014-01-29	1	-105/+305
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*	Added $assert cell	Clifford Wolf	2014-01-19	1	-0/+15
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*	Fixed $lut simlib model for a wider range of tools	Clifford Wolf	2014-01-18	1	-10/+12
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*	More changes to simlib to make it friendlier to a wider range of tools	Clifford Wolf	2014-01-18	1	-10/+14
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*	Fixed a type in $mem model in simlib.v	Clifford Wolf	2014-01-18	1	-1/+1
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*	Added $bu0 cell to simlib.v	Clifford Wolf	2014-01-18	1	-0/+22
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*	Added support for non-const === and !== (for miter circuits)	Clifford Wolf	2013-12-27	1	-0/+36
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*	Renamed stdcells_sim.v to simcells.v and fixed blackbox.v	Clifford Wolf	2013-11-24	1	-8/+8
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*	Cleanups and bugfixes in response to new internal cell checker	Clifford Wolf	2013-11-11	1	-6/+7
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*	Added $sr, $dffsr and $dlatch cell types	Clifford Wolf	2013-10-18	1	-20/+76
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*	Moved common techlib files to techlibs/common	Clifford Wolf	2013-09-15	1	-0/+944