| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fix invalid verilog syntax | Miodrag Milanovic | 2020-03-14 | 1 | -1/+1 |
| * | gate2lut: new techlib, for converting Yosys gates to FPGA LUTs. | whitequark | 2018-12-05 | 1 | -0/+87 |
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index : iCE40/yosys | |
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