| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | make note that it is for latch mode | Miodrag Milanovic | 2019-09-18 | 1 | -0/+1 |
| * | better lut handling | Miodrag Milanovic | 2019-09-18 | 1 | -4/+14 |
| * | Added simulation models for Efinix and Anlogic | Miodrag Milanovic | 2019-09-15 | 1 | -1/+79 |
| * | Fixed Anlogic simulation model | Miodrag Milanovic | 2019-01-25 | 1 | -1/+1 |
| * | Initial support for Anlogic FPGA | Miodrag Milanovic | 2018-12-01 | 1 | -0/+103 |
 |
index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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