| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Removed dbits 8 since 9 will always be picked | Miodrag Milanovic | 2022-01-19 | 1 | -2/+0 |
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| * | anlogic: support BRAM mapping | Icenowy Zheng | 2021-12-17 | 1 | -0/+45 |
| Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being true dual port (or 18bit*512 when simple dual port), the other is 16bit*2K. Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and 32Kbit BRAM with 8bit width are not support yet. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> | |||||
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index : iCE40/yosys | |
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