| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Reduce amount of trailing whitespace in code base | Larry Doolittle | 2019-02-28 | 1 | -3/+3 |
| * | Fix cells_sim.v for Achronix FPGA | Miodrag Milanovic | 2019-01-04 | 1 | -1/+1 |
| * | Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal val... | c60k28 | 2018-03-31 | 1 | -66/+19 |
| * | Organizing Speedster file names | dh73 | 2017-11-08 | 1 | -0/+127 |
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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