iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	alumacc skeleton	Clifford Wolf	2014-09-14	2	-0/+64
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*	Cleanup in wreduce	Clifford Wolf	2014-09-14	1	-11/+8
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*	Added $lcu cell type	Clifford Wolf	2014-09-08	1	-1/+26
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*	Added "$fa" cell type	Clifford Wolf	2014-09-08	2	-6/+47
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*	Trim msb/lsb zero bits from full adder in maccmap	Clifford Wolf	2014-09-08	1	-5/+27
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*	Added "test_cell -const"	Clifford Wolf	2014-09-08	1	-2/+45
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*	Added 'techmap_maccmap' techmap attribute	Clifford Wolf	2014-09-07	1	-19/+53
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*	Added "maccmap" command	Clifford Wolf	2014-09-07	2	-0/+319
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*	Added "test_cell -nosat"	Clifford Wolf	2014-09-07	1	-59/+73
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*	Various bug fixes (related to $macc model testing)	Clifford Wolf	2014-09-06	1	-1/+1
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*	Added $macc SAT model	Clifford Wolf	2014-09-06	1	-5/+6
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*	Added $macc cell type	Clifford Wolf	2014-09-06	1	-2/+53
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*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2014-09-06	9	-15/+15
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\| *	Corrected spelling mistakes found by lintian	Ruben Undheim	2014-09-06	9	-15/+15
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* \|	Added "test_cell -script"	Clifford Wolf	2014-09-06	1	-1/+8
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*	Fixed "opt_const -fine" for $pos cells	Clifford Wolf	2014-09-04	1	-9/+4
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*	Removed $bu0 cell type	Clifford Wolf	2014-09-04	6	-24/+9
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*	Fixed "test_cells -vlog"	Clifford Wolf	2014-09-03	1	-4/+6
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*	Improvements in "test_cell -vlog"	Clifford Wolf	2014-09-02	1	-3/+8
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*	Added test_cell -vlog	Clifford Wolf	2014-09-02	1	-2/+79
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*	Added SAT testing to test_cell eval stage	Clifford Wolf	2014-09-02	1	-1/+89
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*	Removed references to yosys-svgviewer from docs	Clifford Wolf	2014-09-02	1	-2/+2
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*	Using "xdot" instead of "yosys-svgviewer" in show command	Clifford Wolf	2014-09-02	1	-4/+3
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*	Added $alu support to test_cell	Clifford Wolf	2014-09-01	1	-1/+22
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*	Added "test_cell -simlib -v"	Clifford Wolf	2014-09-01	1	-8/+29
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*	Added "techmap -autoproc"	Clifford Wolf	2014-09-01	1	-2/+18
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*	Fixes in old SAT example.ys	Clifford Wolf	2014-09-01	1	-3/+4
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*	Moved "share" and "wreduce" to passes/opt/	Clifford Wolf	2014-09-01	5	-2/+2
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*	Using std::vector<RTLIL::State> instead of RTLIL::Const for ↵	Clifford Wolf	2014-09-01	1	-1/+1
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*	Added eval testing to test_cell	Clifford Wolf	2014-08-31	1	-0/+88
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*	Added $lut support in test_cell, techmap, satgen	Clifford Wolf	2014-08-31	1	-5/+28
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*	Added design->scratchpad	Clifford Wolf	2014-08-30	8	-64/+19
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*	Improved write address decoder generation memory_map	Clifford Wolf	2014-08-30	1	-16/+28
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*	Using worker class in memory_map	Clifford Wolf	2014-08-30	1	-226/+231
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*	Don't change existing binary FSM encoding if it is already optimal	Clifford Wolf	2014-08-30	1	-1/+6
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*	Using $pmux info in fsm_extract to optimize transition ctrl_in patterns	Clifford Wolf	2014-08-30	1	-0/+10
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*	Improved handling of $pmux cells in fsm_extract	Clifford Wolf	2014-08-30	1	-20/+75
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*	Fixed inserting of Q-inverters in dfflibmap	Clifford Wolf	2014-08-27	1	-0/+5
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*	Implemented "rename -enumerate -pattern"	Clifford Wolf	2014-08-26	1	-4/+13
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*	Optimize shift ops with constant rhs in opt_const	Clifford Wolf	2014-08-24	1	-0/+35
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*	Added some additional log messages to opt_const	Clifford Wolf	2014-08-24	1	-1/+10
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*	azonenberg: Make dump_vcd save model when temporal induction fails due to ↵	Clifford Wolf	2014-08-24	1	-0/+2
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*	Only call proc_share_dirname() in techmap when necessary	Clifford Wolf	2014-08-23	1	-2/+1
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*	Changed frontend-api from FILE to std::istream	Clifford Wolf	2014-08-23	7	-38/+47
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*	Changed backend-api from FILE to std::ostream	Clifford Wolf	2014-08-23	2	-97/+98
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*	Added "stat -width"	Clifford Wolf	2014-08-22	1	-4/+37
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*	Added emscripten (emcc) support to build system and some build fixes	Clifford Wolf	2014-08-22	2	-2/+16
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*	Added "plugin" command	Clifford Wolf	2014-08-22	2	-0/+118
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*	Renamed toposort.h to utils.h	Clifford Wolf	2014-08-17	2	-2/+2
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*	Added module->uniquify()	Clifford Wolf	2014-08-16	2	-9/+2
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