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passes
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Author
Age
Files
Lines
*
alumacc skeleton
Clifford Wolf
2014-09-14
2
-0
/
+64
|
*
Cleanup in wreduce
Clifford Wolf
2014-09-14
1
-11
/
+8
|
*
Added $lcu cell type
Clifford Wolf
2014-09-08
1
-1
/
+26
|
*
Added "$fa" cell type
Clifford Wolf
2014-09-08
2
-6
/
+47
|
*
Trim msb/lsb zero bits from full adder in maccmap
Clifford Wolf
2014-09-08
1
-5
/
+27
|
*
Added "test_cell -const"
Clifford Wolf
2014-09-08
1
-2
/
+45
|
*
Added 'techmap_maccmap' techmap attribute
Clifford Wolf
2014-09-07
1
-19
/
+53
|
*
Added "maccmap" command
Clifford Wolf
2014-09-07
2
-0
/
+319
|
*
Added "test_cell -nosat"
Clifford Wolf
2014-09-07
1
-59
/
+73
|
*
Various bug fixes (related to $macc model testing)
Clifford Wolf
2014-09-06
1
-1
/
+1
|
*
Added $macc SAT model
Clifford Wolf
2014-09-06
1
-5
/
+6
|
*
Added $macc cell type
Clifford Wolf
2014-09-06
1
-2
/
+53
|
*
Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf
2014-09-06
9
-15
/
+15
|
\
|
*
Corrected spelling mistakes found by lintian
Ruben Undheim
2014-09-06
9
-15
/
+15
|
|
*
|
Added "test_cell -script"
Clifford Wolf
2014-09-06
1
-1
/
+8
|
/
*
Fixed "opt_const -fine" for $pos cells
Clifford Wolf
2014-09-04
1
-9
/
+4
|
*
Removed $bu0 cell type
Clifford Wolf
2014-09-04
6
-24
/
+9
|
*
Fixed "test_cells -vlog"
Clifford Wolf
2014-09-03
1
-4
/
+6
|
*
Improvements in "test_cell -vlog"
Clifford Wolf
2014-09-02
1
-3
/
+8
|
*
Added test_cell -vlog
Clifford Wolf
2014-09-02
1
-2
/
+79
|
*
Added SAT testing to test_cell eval stage
Clifford Wolf
2014-09-02
1
-1
/
+89
|
*
Removed references to yosys-svgviewer from docs
Clifford Wolf
2014-09-02
1
-2
/
+2
|
*
Using "xdot" instead of "yosys-svgviewer" in show command
Clifford Wolf
2014-09-02
1
-4
/
+3
|
*
Added $alu support to test_cell
Clifford Wolf
2014-09-01
1
-1
/
+22
|
*
Added "test_cell -simlib -v"
Clifford Wolf
2014-09-01
1
-8
/
+29
|
*
Added "techmap -autoproc"
Clifford Wolf
2014-09-01
1
-2
/
+18
|
*
Fixes in old SAT example.ys
Clifford Wolf
2014-09-01
1
-3
/
+4
|
*
Moved "share" and "wreduce" to passes/opt/
Clifford Wolf
2014-09-01
5
-2
/
+2
|
*
Using std::vector<RTLIL::State> instead of RTLIL::Const for ↵
Clifford Wolf
2014-09-01
1
-1
/
+1
|
|
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RTLIL::SigChunk::data
*
Added eval testing to test_cell
Clifford Wolf
2014-08-31
1
-0
/
+88
|
*
Added $lut support in test_cell, techmap, satgen
Clifford Wolf
2014-08-31
1
-5
/
+28
|
*
Added design->scratchpad
Clifford Wolf
2014-08-30
8
-64
/
+19
|
*
Improved write address decoder generation memory_map
Clifford Wolf
2014-08-30
1
-16
/
+28
|
*
Using worker class in memory_map
Clifford Wolf
2014-08-30
1
-226
/
+231
|
*
Don't change existing binary FSM encoding if it is already optimal
Clifford Wolf
2014-08-30
1
-1
/
+6
|
*
Using $pmux info in fsm_extract to optimize transition ctrl_in patterns
Clifford Wolf
2014-08-30
1
-0
/
+10
|
*
Improved handling of $pmux cells in fsm_extract
Clifford Wolf
2014-08-30
1
-20
/
+75
|
*
Fixed inserting of Q-inverters in dfflibmap
Clifford Wolf
2014-08-27
1
-0
/
+5
|
*
Implemented "rename -enumerate -pattern"
Clifford Wolf
2014-08-26
1
-4
/
+13
|
*
Optimize shift ops with constant rhs in opt_const
Clifford Wolf
2014-08-24
1
-0
/
+35
|
*
Added some additional log messages to opt_const
Clifford Wolf
2014-08-24
1
-1
/
+10
|
*
azonenberg: Make dump_vcd save model when temporal induction fails due to ↵
Clifford Wolf
2014-08-24
1
-0
/
+2
|
|
|
|
step limit
*
Only call proc_share_dirname() in techmap when necessary
Clifford Wolf
2014-08-23
1
-2
/
+1
|
*
Changed frontend-api from FILE to std::istream
Clifford Wolf
2014-08-23
7
-38
/
+47
|
*
Changed backend-api from FILE to std::ostream
Clifford Wolf
2014-08-23
2
-97
/
+98
|
*
Added "stat -width"
Clifford Wolf
2014-08-22
1
-4
/
+37
|
*
Added emscripten (emcc) support to build system and some build fixes
Clifford Wolf
2014-08-22
2
-2
/
+16
|
*
Added "plugin" command
Clifford Wolf
2014-08-22
2
-0
/
+118
|
*
Renamed toposort.h to utils.h
Clifford Wolf
2014-08-17
2
-2
/
+2
|
*
Added module->uniquify()
Clifford Wolf
2014-08-16
2
-9
/
+2
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