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* Improved maccmap tree bit packingClifford Wolf2014-09-151-16/+50
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* Fixed wreduce $shiftx handlingClifford Wolf2014-09-151-1/+1
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* Fixed techmap_wrap for techmap_celltypeClifford Wolf2014-09-141-9/+16
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* Various fixes/cleanups in alumacc and maccmapClifford Wolf2014-09-142-2/+11
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* Added techmap_wrap attributeClifford Wolf2014-09-141-5/+28
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* alumacc fix for $pos cellsClifford Wolf2014-09-141-13/+24
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* Extract $alu cells in alumaccClifford Wolf2014-09-141-1/+296
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* Merge $macc cells in alumacc passClifford Wolf2014-09-141-1/+59
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* Basic $macc extract in alumaccClifford Wolf2014-09-141-4/+104
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* alumacc skeletonClifford Wolf2014-09-142-0/+64
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* Cleanup in wreduceClifford Wolf2014-09-141-11/+8
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* Added $lcu cell typeClifford Wolf2014-09-081-1/+26
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* Added "$fa" cell typeClifford Wolf2014-09-082-6/+47
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* Trim msb/lsb zero bits from full adder in maccmapClifford Wolf2014-09-081-5/+27
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* Added "test_cell -const"Clifford Wolf2014-09-081-2/+45
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* Added 'techmap_maccmap' techmap attributeClifford Wolf2014-09-071-19/+53
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* Added "maccmap" commandClifford Wolf2014-09-072-0/+319
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* Added "test_cell -nosat"Clifford Wolf2014-09-071-59/+73
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* Various bug fixes (related to $macc model testing)Clifford Wolf2014-09-061-1/+1
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* Added $macc SAT modelClifford Wolf2014-09-061-5/+6
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* Added $macc cell typeClifford Wolf2014-09-061-2/+53
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* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2014-09-069-15/+15
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| * Corrected spelling mistakes found by lintianRuben Undheim2014-09-069-15/+15
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* | Added "test_cell -script"Clifford Wolf2014-09-061-1/+8
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* Fixed "opt_const -fine" for $pos cellsClifford Wolf2014-09-041-9/+4
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* Removed $bu0 cell typeClifford Wolf2014-09-046-24/+9
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* Fixed "test_cells -vlog"Clifford Wolf2014-09-031-4/+6
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* Improvements in "test_cell -vlog"Clifford Wolf2014-09-021-3/+8
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* Added test_cell -vlogClifford Wolf2014-09-021-2/+79
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* Added SAT testing to test_cell eval stageClifford Wolf2014-09-021-1/+89
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* Removed references to yosys-svgviewer from docsClifford Wolf2014-09-021-2/+2
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* Using "xdot" instead of "yosys-svgviewer" in show commandClifford Wolf2014-09-021-4/+3
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* Added $alu support to test_cellClifford Wolf2014-09-011-1/+22
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* Added "test_cell -simlib -v"Clifford Wolf2014-09-011-8/+29
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* Added "techmap -autoproc"Clifford Wolf2014-09-011-2/+18
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* Fixes in old SAT example.ysClifford Wolf2014-09-011-3/+4
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* Moved "share" and "wreduce" to passes/opt/Clifford Wolf2014-09-015-2/+2
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* Using std::vector<RTLIL::State> instead of RTLIL::Const for ↵Clifford Wolf2014-09-011-1/+1
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* Added eval testing to test_cellClifford Wolf2014-08-311-0/+88
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* Added $lut support in test_cell, techmap, satgenClifford Wolf2014-08-311-5/+28
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* Added design->scratchpadClifford Wolf2014-08-308-64/+19
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* Improved write address decoder generation memory_mapClifford Wolf2014-08-301-16/+28
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* Using worker class in memory_mapClifford Wolf2014-08-301-226/+231
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* Don't change existing binary FSM encoding if it is already optimalClifford Wolf2014-08-301-1/+6
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* Using $pmux info in fsm_extract to optimize transition ctrl_in patternsClifford Wolf2014-08-301-0/+10
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* Improved handling of $pmux cells in fsm_extractClifford Wolf2014-08-301-20/+75
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* Fixed inserting of Q-inverters in dfflibmapClifford Wolf2014-08-271-0/+5
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* Implemented "rename -enumerate -pattern"Clifford Wolf2014-08-261-4/+13
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* Optimize shift ops with constant rhs in opt_constClifford Wolf2014-08-241-0/+35
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* Added some additional log messages to opt_constClifford Wolf2014-08-241-1/+10
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