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* Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-03-256-34/+339
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| * Add "cutpoint" passClifford Wolf2019-03-252-0/+165
| * Merge pull request #896 from YosysHQ/transp_fixesClifford Wolf2019-03-251-9/+16
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| | * memory_bram: Fix multiclock make_transpDavid Shah2019-03-241-9/+16
| * | spaces -> tabsNiels Moseley2019-03-251-78/+78
| * | EOL is now accepted as ';' replacement on lines that look like: feature_xyz(o...Niels Moseley2019-03-251-4/+3
| * | Updated the liberty parser to accept [A:B] ranges (AST has not been updated)....Niels Moseley2019-03-242-7/+90
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| * Add "mutate -none -mode", "mutate -mode none"Clifford Wolf2019-03-231-1/+30
| * Add "mutate -s <filename>"Clifford Wolf2019-03-231-2/+24
* | Cope with SHREG not having E port; Revert $pmux fine tuneEddie Hung2019-03-231-4/+3
* | Add support for SHREGMAP+$mux, also fine tune $pmuxEddie Hung2019-03-221-1/+24
* | Leftover printfEddie Hung2019-03-221-1/+0
* | Fixes for multibitEddie Hung2019-03-221-18/+38
* | Working for 1 bitEddie Hung2019-03-221-11/+49
* | Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-03-221-1/+26
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| * Trim init attributes when resizing FFs in "wreduce", fixes #887Clifford Wolf2019-03-221-1/+26
* | OptEddie Hung2019-03-211-1/+1
* | Fix spacingEddie Hung2019-03-201-239/+239
* | Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable lengthEddie Hung2019-03-191-5/+14
* | Add support for variable length Xilinx SRL > 128Eddie Hung2019-03-191-6/+0
* | shregmap -tech xilinx to delete $shiftx for var length SRLEddie Hung2019-03-191-10/+3
* | Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-03-194-0/+1255
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| * Improve mix of src/wire/wirebit coverage in "mutate -list"Clifford Wolf2019-03-161-29/+84
| * Add "fmcombine -fwd -bwd -nop"Clifford Wolf2019-03-151-10/+59
| * Add fmcombine passClifford Wolf2019-03-152-0/+293
| * Improvements in "mutate" list-reduce algorithmClifford Wolf2019-03-151-13/+36
| * Add "mutate -cfg", improve pick_cover behaviorClifford Wolf2019-03-141-46/+101
| * Add a strictly coverage-driven mutation selection strategyClifford Wolf2019-03-141-1/+70
| * Improve "mutate" wire coverage metricClifford Wolf2019-03-141-1/+16
| * Add more mutation types, improve mutation src coverClifford Wolf2019-03-141-92/+268
| * Add "mutate" command DB reduce functionalityClifford Wolf2019-03-141-12/+181
| * Add "mutate -mode inv", various other mutate improvementsClifford Wolf2019-03-141-99/+213
| * Add basic "mutate -list N" frameworkClifford Wolf2019-03-142-0/+230
| * Improve handling of and-with-1 and or-with-0 in opt_expr, fixes #327Clifford Wolf2019-03-141-0/+7
* | Make output port a non chain userEddie Hung2019-03-191-2/+4
* | Fix shregmap to correctly recognise non chain users; cleanupEddie Hung2019-03-181-17/+15
* | shiftx NULL pointer checkEddie Hung2019-03-181-8/+10
* | CleanupEddie Hung2019-03-161-35/+25
* | Only accept <128 for variable length, only if $shiftx exclusiveEddie Hung2019-03-161-8/+17
* | WorkingEddie Hung2019-03-151-227/+356
* | Revert "Add shregmap -init_msb_first and use in synth_xilinx"Eddie Hung2019-03-141-14/+2
* | Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-03-1410-20/+185
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| * Add $dffsr support to async2syncClifford Wolf2019-03-091-2/+51
| * Fix spelling in pmgen/README.mdEddie Hung2019-03-051-2/+2
| * Only run derive on blackbox modules when ports have dynamic sizeClifford Wolf2019-03-021-1/+1
| * Try again for passes/pmgen/ice40_dsp_pm.h ruleLarry Doolittle2019-03-012-8/+9
| * Fix multiple issues in wreduce FF handling, fixes #835Clifford Wolf2019-02-281-5/+24
| * Reduce amount of trailing whitespace in code baseLarry Doolittle2019-02-281-1/+1
| * Fix pmgen for in-tree buildsClifford Wolf2019-02-282-8/+9
| * Fix pmgen for out-of-tree buildClifford Wolf2019-02-282-4/+6
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