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* Using "xdot" instead of "yosys-svgviewer" in show commandClifford Wolf2014-09-021-4/+3
* Added $alu support to test_cellClifford Wolf2014-09-011-1/+22
* Added "test_cell -simlib -v"Clifford Wolf2014-09-011-8/+29
* Added "techmap -autoproc"Clifford Wolf2014-09-011-2/+18
* Fixes in old SAT example.ysClifford Wolf2014-09-011-3/+4
* Moved "share" and "wreduce" to passes/opt/Clifford Wolf2014-09-015-2/+2
* Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...Clifford Wolf2014-09-011-1/+1
* Added eval testing to test_cellClifford Wolf2014-08-311-0/+88
* Added $lut support in test_cell, techmap, satgenClifford Wolf2014-08-311-5/+28
* Added design->scratchpadClifford Wolf2014-08-308-64/+19
* Improved write address decoder generation memory_mapClifford Wolf2014-08-301-16/+28
* Using worker class in memory_mapClifford Wolf2014-08-301-226/+231
* Don't change existing binary FSM encoding if it is already optimalClifford Wolf2014-08-301-1/+6
* Using $pmux info in fsm_extract to optimize transition ctrl_in patternsClifford Wolf2014-08-301-0/+10
* Improved handling of $pmux cells in fsm_extractClifford Wolf2014-08-301-20/+75
* Fixed inserting of Q-inverters in dfflibmapClifford Wolf2014-08-271-0/+5
* Implemented "rename -enumerate -pattern"Clifford Wolf2014-08-261-4/+13
* Optimize shift ops with constant rhs in opt_constClifford Wolf2014-08-241-0/+35
* Added some additional log messages to opt_constClifford Wolf2014-08-241-1/+10
* azonenberg: Make dump_vcd save model when temporal induction fails due to ste...Clifford Wolf2014-08-241-0/+2
* Only call proc_share_dirname() in techmap when necessaryClifford Wolf2014-08-231-2/+1
* Changed frontend-api from FILE to std::istreamClifford Wolf2014-08-237-38/+47
* Changed backend-api from FILE to std::ostreamClifford Wolf2014-08-232-97/+98
* Added "stat -width"Clifford Wolf2014-08-221-4/+37
* Added emscripten (emcc) support to build system and some build fixesClifford Wolf2014-08-222-2/+16
* Added "plugin" commandClifford Wolf2014-08-222-0/+118
* Renamed toposort.h to utils.hClifford Wolf2014-08-172-2/+2
* Added module->uniquify()Clifford Wolf2014-08-162-9/+2
* Added "test_cell -s <seed>"Clifford Wolf2014-08-161-5/+17
* Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...Clifford Wolf2014-08-161-25/+161
* Added "opt -fast"Clifford Wolf2014-08-161-19/+45
* Bugfix in iopadmapClifford Wolf2014-08-151-1/+3
* Renamed $lut ports to follow A-Y naming schemeClifford Wolf2014-08-151-2/+2
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-155-15/+15
* More idstring sort_by_* helpers and fixed tpl ordering in techmapClifford Wolf2014-08-153-9/+9
* document "techmap -map %<design-name>"Clifford Wolf2014-08-151-0/+3
* Added module->portsClifford Wolf2014-08-144-8/+8
* RIP $safe_pmuxClifford Wolf2014-08-148-9/+7
* Some improvements in FSM mapping and recodingClifford Wolf2014-08-142-8/+16
* Added "abc -D" for setting delay targetClifford Wolf2014-08-141-5/+18
* Filter ANSI escape sequences from ABC outputClifford Wolf2014-08-131-0/+15
* Fixed handling of constant-true branches in proc_cleanClifford Wolf2014-08-122-2/+3
* Fixed FSM mapping for multiple reset-like signalsClifford Wolf2014-08-101-1/+21
* Fixed "share" for complex scenarios with never-active cellsClifford Wolf2014-08-091-6/+22
* Do not share any $reduce_* cells (its complicated and not worth it anyways)Clifford Wolf2014-08-091-19/+0
* Some improvements in fsm_opt and fsm_map for FSM with unreachable statesClifford Wolf2014-08-092-50/+101
* Another fsm_extract bugfixClifford Wolf2014-08-081-0/+4
* Fixed "fsm -export"Clifford Wolf2014-08-082-6/+5
* Fixed sharing of reduce operatorClifford Wolf2014-08-081-0/+13
* Fixed fsm_extract for wreduced muxesClifford Wolf2014-08-081-8/+25
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