iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Improved handling of dff with async resets	Clifford Wolf	2013-10-21	1	-5/+60
*	Added handling of multiple async paths in proc_arst	Clifford Wolf	2013-10-19	2	-8/+21
*	Added dffsr support to proc_dff pass	Clifford Wolf	2013-10-18	1	-7/+72
*	Improved way of connecting ports in techmap pass	Clifford Wolf	2013-10-17	1	-18/+36
*	Only prefer connected signals iff they have public names	Clifford Wolf	2013-10-17	1	-5/+6
*	Fixed bug in synthesis of memories that are never written	Clifford Wolf	2013-10-17	1	-2/+7
*	Avoid re-arranging signals on register outputs	Clifford Wolf	2013-10-17	1	-3/+31
*	Fixed detection of major wires in opt_clean	Clifford Wolf	2013-10-17	1	-0/+3
*	Added iopadmap pass	Clifford Wolf	2013-10-16	3	-1/+161
*	Moved dfflibmap from passes/dfflibmap to passes/techmap	Clifford Wolf	2013-10-16	6	-11/+10
*	Fixed parsing or liberty file statements such as 'clocked_on : "(!CLK)";'	Clifford Wolf	2013-10-16	1	-1/+4
*	Moved common techlib files to techlibs/common	Clifford Wolf	2013-09-15	1	-1/+1
*	Some minor documentation fixes	Clifford Wolf	2013-08-21	2	-2/+2
*	Minor fixes in abc build instructions and abc pass	Clifford Wolf	2013-08-20	1	-4/+4
*	Added sat -ignore_div_by_zero switch	Clifford Wolf	2013-08-15	1	-1/+11
*	Added eval -brute_force_equiv_checker_x mode	Clifford Wolf	2013-08-15	1	-5/+15
*	Added "clean -purge" and ";;;" support	Clifford Wolf	2013-08-11	1	-4/+19
*	Added ";;" as shortcut for "; clean;"	Clifford Wolf	2013-08-11	1	-0/+3
*	freduce performance fix	Clifford Wolf	2013-08-10	1	-4/+8
*	Added techmap -opt mode	Clifford Wolf	2013-08-09	1	-7/+39
*	Some fixes to improve determinism	Clifford Wolf	2013-08-09	3	-30/+33
*	Sort ctrl signals in fsm_extract	Clifford Wolf	2013-08-08	1	-0/+3
*	Added -try option to freduce pass	Clifford Wolf	2013-08-08	1	-16/+44
*	Added "clean" command (less verbose opt_clean)	Clifford Wolf	2013-08-08	1	-9/+52
*	Fixed topological ordering in freduce pass	Clifford Wolf	2013-08-07	1	-54/+67
*	Improved handling of private names in opt_clean and rename commands	Clifford Wolf	2013-08-07	2	-7/+39
*	Small bugfixes in freduce pass	Clifford Wolf	2013-08-06	1	-4/+14
*	Added freduce command	Clifford Wolf	2013-08-06	2	-0/+362
*	Added "design" command (-reset, -save, -load)	Clifford Wolf	2013-07-27	2	-0/+129
*	Automatically run "proc" on extract map files	Clifford Wolf	2013-07-24	1	-0/+5
*	Added $lut cells and abc lut mapping support	Clifford Wolf	2013-07-23	4	-14/+255
*	Bugfixes for empty signal vectors	Clifford Wolf	2013-07-10	1	-0/+3
*	Added opt_clean -purge option	Clifford Wolf	2013-07-07	1	-7/+19
*	Fixed handling of $eq and $ne in opt_const	Clifford Wolf	2013-07-07	1	-2/+2
*	Added SAT support for -all/-max with -verify	Clifford Wolf	2013-06-23	1	-6/+11
*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2013-06-20	1	-2/+28
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\| *	Added renaming of wires and cells to "rename" command	Clifford Wolf	2013-06-19	1	-2/+28
* \|	Added timout functionality to SAT solver	Clifford Wolf	2013-06-20	1	-5/+62
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*	Added "eval" pass	Clifford Wolf	2013-06-19	3	-187/+228
*	Added splitnets command	Clifford Wolf	2013-06-18	2	-0/+110
*	Added support for "assign" statements in abc vlparse	Clifford Wolf	2013-06-15	2	-2/+39
*	Fixed even more ConstEval bugs found using xsthammer	Clifford Wolf	2013-06-14	1	-2/+1
*	Added consteval testing to xsthammer and fixed bugs	Clifford Wolf	2013-06-13	1	-0/+97
*	More xsthammer improvements (using xst 14.5 now)	Clifford Wolf	2013-06-13	1	-1/+1
*	Added "scatter" command	Clifford Wolf	2013-06-12	2	-0/+73
*	Renamed yosys-show temp files to be dot-files in the users home directory	Clifford Wolf	2013-06-12	1	-3/+3
*	Improvements and fixes in SAT code	Clifford Wolf	2013-06-10	1	-4/+14
*	Added "rename" command	Clifford Wolf	2013-06-10	2	-0/+95
*	Renamed "sat_solve" pass to "sat"	Clifford Wolf	2013-06-09	3	-13/+13
*	Implemented temporal induction proofs in sat_solve	Clifford Wolf	2013-06-09	2	-37/+178